Low temperature mobility improvement in high-mobility strained-Si/Si1-xGex multilayer MOSFETs

1998 ◽  
Vol 08 (PR3) ◽  
pp. Pr3-57-Pr3-60
Author(s):  
J. B. Roldán ◽  
F. Gámiz ◽  
J. A. López-Villanueva ◽  
J. E. Carceller
2002 ◽  
Vol 745 ◽  
Author(s):  
Gianni Taraschi ◽  
Arthur J. Pitera ◽  
Lisa M. McGill ◽  
Zhi-Yuan Cheng ◽  
Minjoo L. Lee ◽  
...  

ABSTRACTAdvanced CMOS substrates composed of ultra-thin strained-Si and SiGe-on-insulator were fabricated, combining both the benefits of high-mobility strained-Si and SOI. Our pioneering method employed wafer bonding of SiGe virtual substrates (with strained-Si layers) to oxidized handle wafers. Layer transfer onto insulating handle wafers can be accomplished using grind-etchback or delamination via implantation. Both methods were found to produce a rough transferred layer, but polishing is unacceptable due to non-uniform material removal across the wafer and the lack of precise control over the final layer thickness. To solve these problems, a strained-Si stop layer was incorporated into the bonding structure. After layer transfer, excess SiGe was removed using a selective etch process, stopping on the strained-Si. Within the context of ultra-thin SSOI and SGOI fabrication, this paper describes recent improvements including metastable stop layers, low temperature wafer bonding, and improved selective SiGe removal.


1989 ◽  
Vol 36 (9) ◽  
pp. 1929-1933 ◽  
Author(s):  
T. Serikawa ◽  
S. Shirai ◽  
A. Okamoto ◽  
S. Suyama

2021 ◽  
Vol 42 (10) ◽  
pp. 1480-1483
Author(s):  
Yining Yu ◽  
Nannan Lv ◽  
Dongli Zhang ◽  
Yiran Wei ◽  
Mingxiang Wang

2020 ◽  
Vol 2 (7) ◽  
pp. 1997-2002
Author(s):  
Debarghya Sarkar ◽  
Jun Tao ◽  
Ragib Ahsan ◽  
Dingzhu Yang ◽  
Thomas Orvis ◽  
...  

2019 ◽  
Vol 58 (9) ◽  
pp. 090605
Author(s):  
Kosuke Takenaka ◽  
Masashi Endo ◽  
Hiroyuki Hirayama ◽  
Giichiro Uchida ◽  
Akinori Ebe ◽  
...  

Author(s):  
Mehdi Asheghi

There have been many attempts in the recent years to improve the device performance by enhancing carrier mobility by using the strained-induced changes in silicon electronic bands [1–4] or reducing the junction capacitance in silicon-on-insulator (SOI) technology. Strained silicon on insulator (SSOI) is another promising technology, which is expected to show even higher performance, in terms of speed and power consumption, comparing to the regular strained-Si transistors. In this technology, the strained silicon is incorporated in the silicon on insulator (SOI) technology such that the strained-Si introduces high mobility for electrons and holes and the insulator layer (usually SiO2) exhibits low junction capacitance due to its small dielectric constant [5, 6]. In these devices a layer of SiGe may exist between the strined-Si layer and insulator (strained Si-on-SiGe-on-insulator, SGOI) [6] or the strained-Si layer can be directly on top of the insulator [7]. Latter is advantageous for eliminating some of the key problems associated with the fabrication of SGOI.


2016 ◽  
Vol 10 (6) ◽  
pp. 493-497 ◽  
Author(s):  
Peng Xiao ◽  
Ting Dong ◽  
Linfeng Lan ◽  
Zhenguo Lin ◽  
Wei Song ◽  
...  

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