Thermal Stress in CVD PSG and SiO2 Films on Silicon Substrates

1983 ◽  
Vol 130 (1) ◽  
pp. 135-138 ◽  
Author(s):  
M. Shimbo ◽  
T. Matsuo
Keyword(s):  
Thermal Stress ◽  
Silicon Substrates ◽  
Sio2 Films

THERMAL STRESS RELAXATION BY A COMPOSITION-GRADED INTERMEDIATE LAYER

2000 ◽  
Vol 14 (19) ◽  
pp. 685-692 ◽  
Author(s):  
Q.-R. HOU ◽  
J. GAO
Keyword(s):  
Thermal Stress ◽  
Stress Distribution ◽  
Intermediate Layer ◽  
Carbon Films ◽  
Composition Profile ◽  
Thin Layers ◽  
Diamond Like Carbon ◽  
Silicon Substrates ◽  
Adjacent Layer ◽  
Thermal Stress Distribution

A simple model has been proposed to calculate the thermal stress distribution for diamond-like carbon films deposited on silicon substrates with a composition-graded intermediate layer. In this model, the intermediate layer is divided into many thin layers, and the thermal stress in one thin layer is caused by the difference in thermal expansion coefficients between this layer and the adjacent layer. It is found that the thermal stress distribution in the intermediate layer is strongly dependent on the composition profile of the intermediate layer. By choosing a proper composition profile, the thermal stress near the interlayer/substrate interface will be very small and this small stress is beneficial to enhancing adhesion of the film. For diamond-like carbon films deposited on silicon substrates, the experimental results are in agreement with the theoretical prediction qualitatively.

Study of Thermal Stress in Nano Silver Bonded Silicon Substrates for High Temperature Applications

2019 ◽  
Vol 2019 (HiTen) ◽  
pp. 000052-000055
Author(s):  
G.D. Liu ◽  
C.H. Wang
Keyword(s):  
Thermal Stress ◽  
High Temperature ◽  
Silver Layer ◽  
Silicon Substrates ◽  
The Finite Element Method ◽  
Nano Silver ◽  
Silicon Chips ◽  
Die Attach ◽  
The Relationship ◽  
Sintered Silver

Abstract The silver nanoparticle paste is a promising material for high temperature die-attach applications. In this paper, the finite element method is used to study the relationship between the thickness of the sintered silver layer and the thermal stress in the sintered silver joint. Silicon chips are bonded together with sintered silver layers of different thicknesses. In the experimental study, strain gauges are attached onto the surface of the upper silicon and used to estimate the effects of the nano silver die-attach layer. The results show that the average stress in the silver layer at the interface decreases with the increasing thickness of the silver layer, while the stress on the silicon surface increases with the increasing thickness of the silver layer.

Mechanisms of Stress-Induced and Electromigration-Induced Damage in Passivated Narrow Metallizations on Rigid Substrates

MRS Bulletin ◽  
1992 ◽  
Vol 17 (7) ◽  
pp. 61-69 ◽  
Author(s):  
M.A. Korhonen ◽  
P. Børgesen ◽  
Che-Yu Li
Keyword(s):  
Thermal Stress ◽  
Thermal Stresses ◽  
Elevated Temperatures ◽  
Semiconductor Industry ◽  
Pure Aluminum ◽  
Void Formation ◽  
Silicon Substrates ◽  
Thermal Expansion Coefficients ◽  
Hillock Formation ◽  
Current Densities

Narrow, passivated metal lines are generally used as interconnects in VLSI microcircuits at the chip level. In most metals, high electric current densities lead to a mass flow of constituent atoms accompanying the current of electrons. Electromigration (EM) has long been considered an important reliability concern in the semiconductor industry because the current-induced atomic fluxes can give rise to void formation and open circuits, or hillock formation and short circuits between nearby interconnects. The problem is exacerbated because of the continued trend of increasing the density of the devices on the chip. This means that the line widths of the interconnects have been reduced and are now in the submicron range; correspondingly, the current densities have increased and may be as high as 106 A/cm2. Recently, thermal-stress-induced damage in metallizations has also been recognized as an important reliability concern, perhaps of the same gravity as EM. Thermal stresses in the metallizations are caused by the different thermal expansion coefficients of the metal and the substrate. Stress-induced void and hillock formation are the main causes of in terconnect failures before service. More recently, concern has been growing that thermal stresses or thermal-stress-induced voids may enhance the subsequent electromigration damage during the service life of the microchips.For simplicity, this article addresses the case of pure aluminum metallizations on oxidized silicon substrates. However, much of what is said applies to other metal-rigid substrate systems as well, most notably to various aluminum and copper-based metallizations on ceramic substrates. The present treatment emphasizes void formation and growth in the metallizations during nd after cooldown from elevated temperatures, or those due to electromigration in service or testing conditions. Many of the mechanisms we explain are also applicable to hillock formation under compressive stresses, whether due to EM or thermal cycles during manufacturing.

scholarly journals Thermal stress and deformation in a copper film on silicon substrates

2003 ◽  
Vol 2003 (0) ◽  
pp. 81-82
Author(s):  
Hideo TAKAHASHI ◽  
Masahiro UETAKE ◽  
Goroh ITOH ◽  
Junich KOIKE
Keyword(s):  
Thermal Stress ◽  
Copper Film ◽  
Silicon Substrates ◽  
Stress And Deformation

Microhardness of Thin SIO2 Films On Silicon.

1991 ◽  
Vol 226 ◽  
Author(s):  
B. Yost ◽  
Che-Yu Li ◽  
Bette Bergman-Reuter ◽  
Tim Sullivan
Keyword(s):  
Residual Stress ◽  
Silicon Substrates ◽  
Sio2 Films ◽  
Stress Levels ◽  
Thermal Histories

AbstractHardness properties of CVD SiO2, films deposited on silicon substrates are investigated by microindentation techniques. It is found that the hardness of these films is sensitive to the thermal histories and doping and is less influenced by the residual stress levels.

Electron Energy Analysis of Germanium and Silica Layers on Silicon Substrates

1975 ◽  
Vol 33 ◽  
pp. 96-97
Author(s):  
R. W. Ditchfield ◽  
A. G. Cullis
Keyword(s):  
Epitaxial Growth ◽  
Electron Energy ◽  
Silicon Substrates ◽  
Secondary Phases ◽  
Si Substrates ◽  
Transmission Electron ◽  
Layer Structures ◽  
Si Films ◽  
Electron Energy Loss ◽  
Growth Centres

An energy analyzing transmission electron microscope of the Möllenstedt type was used to measure the electron energy loss spectra given by various layer structures to a spatial resolution of 100Å. The technique is an important, method of microanalysis and has been used to identify secondary phases in alloys and impurity particles incorporated into epitaxial Si films.Layers Formed by the Epitaxial Growth of Ge on Si Substrates Following studies of the epitaxial growth of Ge on (111) Si substrates by vacuum evaporation, it was important to investigate the possible mixing of these two elements in the grown layers. These layers consisted of separate growth centres which were often triangular and oriented in the same sense, as shown in Fig. 1.

Characterization of Y-Ba-Cu-O films grown on silicon substrates by sequential evaporation

1988 ◽  
Vol 46 ◽  
pp. 866-867
Author(s):  
E. L. Hall ◽  
A. Mogro-Campero ◽  
L. G. Turner ◽  
N. Lewis
Keyword(s):  
Thin Film ◽  
Thin Film Deposition ◽  
Superconducting Films ◽  
Electron Beam Evaporation ◽  
Film Deposition ◽  
Silicon Substrates ◽  
Superconducting Properties ◽  
Sequential Electron ◽  
Thin Superconducting Films

There is great interest in the growth of thin superconducting films of YBa2Cu3Ox on silicon, since this is a necessary first step in the use of this superconductor in a variety of possible electronic applications including interconnects and hybrid semiconductor/superconductor devices. However, initial experiments in this area showed that drastic interdiffusion of Si into the superconductor occurred during annealing if the Y-Ba-Cu-O was deposited direcdy on Si or SiO2, and this interdiffusion destroyed the superconducting properties. This paper describes the results of the use of a zirconia buffer layer as a diffusion barrier in the growth of thin YBa2Cu3Ox films on Si. A more complete description of the growth and characterization of these films will be published elsewhere.Thin film deposition was carried out by sequential electron beam evaporation in vacuum onto clean or oxidized single crystal Si wafers. The first layer evaporated was 0.4 μm of zirconia.

Formation of defects in implanted hipox-structures

1992 ◽  
Vol 50 (2) ◽  
pp. 1406-1407
Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan
Keyword(s):  
High Pressure ◽  
Cross Section ◽  
Semiconductor Devices ◽  
Silicon Substrates ◽  
Processing Conditions ◽  
Pressure Oxidation ◽  
Deep Trench ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.

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