scholarly journals Method for Measuring Deep Levels in Thin Silicon‐on‐Insulator Layer Without Any Interface Effects

1998 ◽  
Vol 145 (10) ◽  
pp. 3581-3585 ◽  
Author(s):  
H. S. Kang ◽  
C. G. Ahn ◽  
B. K. Kang ◽  
Y. K. Kwon
Keyword(s):  
Deep Levels ◽  
Silicon On Insulator ◽  
Insulator Layer ◽  
Thin Silicon ◽  
Interface Effects

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Formation technology of flat surface with epitaxial growth on ion-implanted (100)-oriented Si surface of thin silicon-on-insulator

2017 ◽  
Vol 56 (10) ◽  
pp. 105503
Author(s):  
Kiichi Furukawa ◽  
Akinobu Teramoto ◽  
Rihito Kuroda ◽  
Tomoyuki Suwa ◽  
Keiichi Hashimoto ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Flat Surface ◽  
Silicon On Insulator ◽  
Thin Silicon ◽  
Ion Implanted

scholarly journals Анодное окисление слоев кремний-на-изоляторе, созданных методом водородного переноса

2019 ◽  
Vol 53 (2) ◽  
pp. 253
Author(s):  
И.Е. Тысченко ◽  
И.В. Попов ◽  
Е.В. Спесивцев
Keyword(s):  
Oxidation Rate ◽  
Hydrogen Transfer ◽  
Single Crystal Silicon ◽  
Interatomic Interaction ◽  
Surface Region ◽  
Bound State ◽  
Silicon On Insulator ◽  
Bulk Single Crystal ◽  
Crystal Silicon ◽  
Insulator Layer

AbstractThe anodic oxidation rate of silicon-on-insulator films fabricated by hydrogen transfer is studied as a function of the temperature of subsequent annealing. It is established that the oxidation rate of transferred silicon-on-insulator films is five times lower compared to the oxidation rate of bulk single-crystal silicon samples. The oxidation rate increases, as the annealing temperature is elevated in the range 700–1100°C and as the depth of gradually removed anode-oxidized layers is increased. The results obtained in the study are attributed to an increase in the efficiencies of the anodic current and oxygen–silicon interatomic interaction due to the annealing of defects and due to release of hydrogen from the bound state, respectively. The formation of hydrogen bubbles in the surface region of silicon due to the diffusion of hydrogen, released in the process of the oxidation reaction, towards micropores in the silicon-on-insulator layer is detected.

Computer Simulation for the Formation of the Insulator Layer of Silicon-on-Insulator Devices by N + and O + Co-implantation

2002 ◽  
Vol 19 (12) ◽  
pp. 1782-1784 ◽  
Author(s):  
Lin Qing ◽  
Zhu Ming ◽  
Liu Xiang-Hua ◽  
Xie Xin-Yun ◽  
Lin Cheng-Lu
Keyword(s):  
Computer Simulation ◽  
Silicon On Insulator ◽  
Insulator Layer

Fabrication of thin silicon-on-insulator flims using laser recrystallisation

1985 ◽  
Vol 21 (23) ◽  
pp. 1102 ◽  
Author(s):  
J.P. Colinge ◽  
H.K. Hu ◽  
S. Peng
Keyword(s):  
Silicon On Insulator ◽  
Thin Silicon

Diffusion of Silicon Interstitials in thin Silicon Films on Insulator in Neutral and Oxidising Annealing Ambients

1997 ◽  
Vol 469 ◽  
Author(s):  
Guénolé C.M. Silvestre
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Annealing Treatment ◽  
Silicon On Insulator ◽  
Buried Oxide ◽  
Thermal Oxide ◽  
Good Crystalline Quality ◽  
Thin Silicon ◽  
Experimental Values ◽  
Fault Growth

ABSTRACTSilicon-On-Insulator (SOI) materials have emerged as a very promising technology for the fabrication of high performance integrated circuits since they offer significant improvement to device performance. Thin silicon layers of good crystalline quality are now widely available on buried oxide layers of various thicknesses with good insulating properties. However, the SOI structure is quite different from that of bulk silicon. This paper will discuss a study of point-defect diffusion and recombination in thin silicon layers during high temperature annealing treatment through the investigation of stacking-fault growth kinetics. The use of capping layers such as nitride, thin thermal oxide and thick deposited oxide outlines the diffusion mechanisms of interstitials in the SOI structure. It also shows that the buried oxide layer is a very good barrier to the diffusion of point defects and that excess silicon interstitials may be reincorporated at the top interface with the thermal oxide through the formation of SiO species. Finally, from the experimental values of the activation energies for the growth and the shrinkage of stacking-faults, the energy of interstitial creation is evaluated to be 2.6 eV, the energy for interstitial migration to be 1.8 eV and the energy of interstitial generation during oxidation to be 0.2 eV.

Nanoparticle Scattering, Absorption, and Interface Effects for Surface Plasmon Enhanced Thin Silicon Solar Cells

2013 ◽  
pp. 210-230
Author(s):  
Nirag Kadakia
Keyword(s):  
Solar Cells ◽  
Surface Plasmons ◽  
Metal Nanoparticle ◽  
Silicon Solar Cells ◽  
Silicon Devices ◽  
Silicon Photovoltaics ◽  
Thin Silicon ◽  
Embedding Medium ◽  
Plasmonic Solar Cells ◽  
Interface Effects

Recently, surface plasmons have been employed in a variety of methods to increase the efficiency of solar cells. Surface plasmons are oscillations of electrons that arise from surface effects of light interaction with materials that have appreciable free carrier densities; their resonance is confined to a region that depends on the dielectric response of the medium. It has been observed that noble metals exhibit this resonance within visible- near IR range, making them an attractive candidate for silicon solar cells whose primary absorption bands are in this region. Research in silicon-based plasmonic solar cells has utilized the high scattering cross section and favorable angular distributions of noble metal nanoparticle-scattered radiation to increase absorption of thin silicon devices, which are normally weakly absorbing for photons of energy below 2 eV. The interaction is subject to interface effects, interferences of scattered and incident radiation, and the dielectric nature of the embedding medium or surface. In addition, perturbations caused by the longitudinal field of the metal nanoparticle may theoretically enhance the direct interband transitions of free carriers near the particle surface, further enhancing the photocurrent. This latter possibility has yet to be fully explored experimentally in crystalline silicon photovoltaics.

Doping Measurements in Thin Silicon‐On‐Insulator Films

1999 ◽  
Vol 146 (7) ◽  
pp. 2737-2743 ◽  
Author(s):  
S. Hénaux ◽  
F. Mondon ◽  
F. Gusella ◽  
I. Kling ◽  
G. Reimbold
Keyword(s):  
Silicon On Insulator ◽  
Thin Silicon

Nanoscale Heat Conduction in the SOI, Strained-Si and Tri-Gate Transistors

2004 ◽  
Author(s):  
Mehdi Asheghi
Keyword(s):  
Carrier Mobility ◽  
High Mobility ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Device Performance ◽  
Strained Si ◽  
Insulator Layer ◽  
Junction Capacitance ◽  
Induced Changes ◽  
Soi Technology

There have been many attempts in the recent years to improve the device performance by enhancing carrier mobility by using the strained-induced changes in silicon electronic bands [1–4] or reducing the junction capacitance in silicon-on-insulator (SOI) technology. Strained silicon on insulator (SSOI) is another promising technology, which is expected to show even higher performance, in terms of speed and power consumption, comparing to the regular strained-Si transistors. In this technology, the strained silicon is incorporated in the silicon on insulator (SOI) technology such that the strained-Si introduces high mobility for electrons and holes and the insulator layer (usually SiO2) exhibits low junction capacitance due to its small dielectric constant [5, 6]. In these devices a layer of SiGe may exist between the strined-Si layer and insulator (strained Si-on-SiGe-on-insulator, SGOI) [6] or the strained-Si layer can be directly on top of the insulator [7]. Latter is advantageous for eliminating some of the key problems associated with the fabrication of SGOI.

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