Low Temperature Nafion Bonding of Silicon Wafers

1999 ◽  
Vol 2 (2) ◽  
pp. 86 ◽  
Author(s):  
B. Ilic
Keyword(s):  
Low Temperature ◽  
Silicon Wafers

Low temperature drive-in of surface-deposited copper in silicon wafers

2004 ◽  
Vol 27 (1-3) ◽  
pp. 435-438 ◽  
Author(s):  
M. L. Polignano ◽  
D. Caputo ◽  
C. Carpanese ◽  
G. Salvà ◽  
L. Vanzetti
Keyword(s):  
Low Temperature ◽  
Silicon Wafers

Carrier Lifetime Measurements by Photoconductance at Low Temperature on Passivated Crystalline Silicon Wafers

2013 ◽  
Vol 1536 ◽  
pp. 119-125 ◽  
Author(s):  
Guillaume Courtois ◽  
Bastien Bruneau ◽  
Igor P. Sobkowicz ◽  
Antoine Salomon ◽  
Pere Roca i Cabarrocas
Keyword(s):  
Low Temperature ◽  
Electron Mobility ◽  
Carrier Density ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Silicon Wafers ◽  
Doping Density ◽  
Lifetime Measurements ◽  
Effective Lifetime

ABSTRACTWe propose an implementation of the PCD technique to minority carrier effective lifetime assessment in crystalline silicon at 77K. We focus here on (n)-type, FZ, polished wafers passivated by a-Si:H deposited by PECVD at 200°C. The samples were immersed into liquid N2 contained in a beaker placed on a Sinton lifetime tester. Prior to be converted into lifetimes, data were corrected for the height shift induced by the beaker. One issue lied in obtaining the sum of carrier mobilities at 77K. From dark conductance measurements performed on the lifetime tester, we extracted an electron mobility of 1.1x104 cm².V-1.s-1 at 77K, the doping density being independently calculated in order to account for the freezing effect of dopants. This way, we could obtain lifetime curves with respect to the carrier density. Effective lifetimes obtained at 77K proved to be significantly lower than at RT and not to depend upon the doping of the a-Si:H layers. We were also able to experimentally verify the expected rise in the implied Voc, which, on symmetrically passivated wafers, went up from 0.72V at RT to 1.04V at 77K under 1 sun equivalent illumination.

The Effect of Ultra-Low Temperature Treatments on the Stress in Aluminum Metallization on Silicon Wafers

1994 ◽  
Vol 338 ◽  
Author(s):  
Frank Baldwin ◽  
Paul H. Holloway ◽  
Mark Bordelon ◽  
Thomas R. Watkins
Keyword(s):  
Stress Relaxation ◽  
Low Temperature ◽  
Thermal Cycling ◽  
Liquid Nitrogen ◽  
Room Temperature ◽  
Silicon Wafers ◽  
X Ray Diffraction ◽  
X Ray ◽  
Aluminum Metallization ◽  
Low Temperature Treatments

ABSTRACTThe stresses in Al-0.75w%Si-0.5w%Cu unpatterned metallization on silicon wafers have been measured using substrate curvature and x-ray diffraction techniques after quenching in liquid nitrogen. Stresses were measured with and without phospho-silicate glass overlayers and SiO2 underlayers, and thermal cycling followed by relaxation at room temperature. It was found that cooling the substrates to 77 K and warming to room temperature caused the metallization stress to go from tensile to compressive. Subsequent heating of the substrates to above ∼70°C followed by cooling to room temperature caused the stress to become tensile. Both compressive and tensile stresses were found to relax at room temperature with a time constant of 2.3 ± 0.2 hours. The magnitude of stress relaxation was a function of temperature, being about 20 MPa after heating to 240°C. The metallization exhibited both compressive and tensile flow stresses of ∼100 MPa near room temperature.

Study of low-temperature direct bonding of (111) and (100) silicon wafers under various ambient and surface conditions

2000 ◽  
Vol 80 (1) ◽  
pp. 68-76 ◽  
Author(s):  
Drago Resnik ◽  
Danilo Vrtačnik ◽  
Uroš Aljančič ◽  
Slavko Amon
Keyword(s):  
Low Temperature ◽  
Silicon Wafers ◽  
Surface Conditions

Low-temperature anodic bonding of silicon to silicon wafers by means of intermediate glass layers

1999 ◽  
Vol 5 (3) ◽  
pp. 144-149 ◽  
Author(s):  
A. Gerlach ◽  
D. Maas ◽  
D. Seidel ◽  
H. Bartuch ◽  
S. Schundau ◽  
...  
Keyword(s):  
Low Temperature ◽  
Silicon Wafers ◽  
Anodic Bonding

Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

2009 ◽  
Vol 159-160 ◽  
pp. 242-247 ◽  
Author(s):  
A. Focsa ◽  
A. Slaoui ◽  
H. Charifi ◽  
J.P. Stoquert ◽  
S. Roques
Keyword(s):  
Low Temperature ◽  
Double Layer ◽  
Surface Passivation ◽  
Silicon Wafers ◽  
Type Silicon
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