Low-temperature anodic bonding of silicon to silicon wafers by means of intermediate glass layers

1999 ◽  
Vol 5 (3) ◽  
pp. 144-149 ◽  
Author(s):  
A. Gerlach ◽  
D. Maas ◽  
D. Seidel ◽  
H. Bartuch ◽  
S. Schundau ◽  
...  
Keyword(s):  
Low Temperature ◽  
Silicon Wafers ◽  
Anodic Bonding

Low temperature drive-in of surface-deposited copper in silicon wafers

2004 ◽  
Vol 27 (1-3) ◽  
pp. 435-438 ◽  
Author(s):  
M. L. Polignano ◽  
D. Caputo ◽  
C. Carpanese ◽  
G. Salvà ◽  
L. Vanzetti
Keyword(s):  
Low Temperature ◽  
Silicon Wafers

Carrier Lifetime Measurements by Photoconductance at Low Temperature on Passivated Crystalline Silicon Wafers

2013 ◽  
Vol 1536 ◽  
pp. 119-125 ◽  
Author(s):  
Guillaume Courtois ◽  
Bastien Bruneau ◽  
Igor P. Sobkowicz ◽  
Antoine Salomon ◽  
Pere Roca i Cabarrocas
Keyword(s):  
Low Temperature ◽  
Electron Mobility ◽  
Carrier Density ◽  
Carrier Lifetime ◽  
Minority Carrier ◽  
Crystalline Silicon ◽  
Silicon Wafers ◽  
Doping Density ◽  
Lifetime Measurements ◽  
Effective Lifetime

ABSTRACTWe propose an implementation of the PCD technique to minority carrier effective lifetime assessment in crystalline silicon at 77K. We focus here on (n)-type, FZ, polished wafers passivated by a-Si:H deposited by PECVD at 200°C. The samples were immersed into liquid N2 contained in a beaker placed on a Sinton lifetime tester. Prior to be converted into lifetimes, data were corrected for the height shift induced by the beaker. One issue lied in obtaining the sum of carrier mobilities at 77K. From dark conductance measurements performed on the lifetime tester, we extracted an electron mobility of 1.1x104 cm².V-1.s-1 at 77K, the doping density being independently calculated in order to account for the freezing effect of dopants. This way, we could obtain lifetime curves with respect to the carrier density. Effective lifetimes obtained at 77K proved to be significantly lower than at RT and not to depend upon the doping of the a-Si:H layers. We were also able to experimentally verify the expected rise in the implied Voc, which, on symmetrically passivated wafers, went up from 0.72V at RT to 1.04V at 77K under 1 sun equivalent illumination.

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

Low-temperature anodic bonding using thin films of lithium-niobate-phosphate glass

2014 ◽  
Vol 24 (9) ◽  
pp. 095001 ◽  
Author(s):  
S Woetzel ◽  
E Kessler ◽  
M Diegel ◽  
V Schultze ◽  
H-G Meyer
Keyword(s):  
Thin Films ◽  
Low Temperature ◽  
Lithium Niobate ◽  
Phosphate Glass ◽  
Anodic Bonding

Bonding of 2 mm thick silicon wafers using LTCC as an intermediate layer

2012 ◽  
Vol 2012 (CICMT) ◽  
pp. 000436-000440 ◽  
Author(s):  
S. Günschmann ◽  
M. Fischer ◽  
T. Bley ◽  
I. Käpplinger ◽  
W. Brode ◽  
...  
Keyword(s):  
High Pressure ◽  
Wafer Bonding ◽  
Silicon Surface ◽  
Silicon Wafers ◽  
Anodic Bonding ◽  
Silicon Substrates ◽  
Infrared Transmission ◽  
Fusion Bonding ◽  
Internal Side ◽  
Bonding Technique

For the fabrication of a micro fluidic high pressure oil sensor (400 bar) based on an infrared transmission measuring principle the bonding of 2 mm silicon wafers is necessary. Conventional bonding techniques such as silicon fusion bonding or anodic bonding are not suitable for bonding thick and inflexible silicon wafers, because these techniques can not compensate for the wafer bow. We present a new bonding procedure for silicon substrates thicker than 1 mm using a silicon adapted LTCC tape as an intermediate leveling layer. The wafers are preprocessed by etching a nano structured silicon surface on the internal side. The silicon wafers are aligned and stacked with pre-structured green LTCC tapes by an optical stacking unit. During the hot isostatic lamination at 55 bar the structured LTCC tape is adjusted to the silicon. A subsequent pressure assisted sintering leads to a wafer bonding strength up to 5000 N/cm2. With the bonding technique it is possible to create cavities and channels between the thick wafers by the use of punched and laser cut LTCC. The fabrication steps of the sandwich build-up especially the sequential lamination and the optical adjusting procedure of the flexible (LTCC) and inflexible (2 mm Wafer) substrates will be explained in detail. A method to reduce the shrinkage and distortion of the green LTCC during handling is demonstrated. The distribution of the bonding and bursting strength of the single fluidic systems on a complete sandwich substrate is analyzed.

Low Temperature Anodic Bonding for MEMS Applications

2002 ◽  
Author(s):  
J. Wei ◽  
Z. P. Wang ◽  
L. Wang ◽  
G. Y. Li ◽  
Z. Q. Mo
Keyword(s):  
Low Temperature ◽  
Bonding Strength ◽  
Transition Period ◽  
Bonding Temperature ◽  
Testing Machine ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
Dominant Factor ◽  
Glass Wafer ◽  
Bonding Parameters

In this paper, anodic bonding between silicon wafer and glass wafer (Pyrex 7740) has been successfully achieved at low temperature. The bonding strength is measured using a tensile testing machine. The interfaces are examined and analyzed by scanning acoustic microscopy (SAM), scanning electron microscopy (SEM) and secondary ion mass spectrometry (SIMS). Prior to bonding, the wafers are cleaned in RCA solutions, and the surfaces become hydrophilic. The effects of the bonding parameters, such as bonding temperature, voltage, bonding time and vacuum condition, on bonding quality are investigated using Taguchi method, and the feasibility of bonding silicon and glass wafers at low temperature is explored. The bonding temperature used ranges from 200 °C to 300 °C. The sensitivity of the bonding parameters is analyzed and it is found that the bonding temperature is the dominant factor for the bonding process. Therefore, the effects of bonding temperature are investigated in detail. High temperatures cause high ion mobility and bonding current density, resulting in the short transition period to the equilibrium state. Almost bubble-free interfaces have been obtained. The bonded area increases with increasing the bonding temperature. The unbonded area is less than 1.5% within the whole wafer for bonding temperature between 200 °C to 300 °C. The bonding strength is higher than 10 MPa, and increases with the bonding temperature. Fracture mainly occurs inside the glass wafer other than in the interface when the bonding temperature is higher than 225 °C. SIMS results show that the chemical bonds of Si-O form in the interface. Higher bonding temperature results in more oxygen migration to the interface and more Si-O bonds. The bonding mechanisms consist of hydrogen bonding and Si-O chemical reaction.

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