Via Impact on the Upstream Electromigration of 40/45nm Low-k Cu Interconnect

X. F. Zhao; J. Wu; V. Chang

doi:10.1149/06001.0933ecst

Via Impact on the Upstream Electromigration of 40/45nm Low-k Cu Interconnect

ECS Transactions ◽

10.1149/06001.0933ecst ◽

2014 ◽

Vol 60 (1) ◽

pp. 933-937 ◽

Cited By ~ 1

Author(s):

X. F. Zhao ◽

J. Wu ◽

V. Chang

Keyword(s):

Cu Interconnect ◽

Low K

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Qualification of Resist Strip Process for Ultra Low-k/Cu Interconnect

Solid State Phenomena - Ultra Clean Processing of Silicon Surfaces VII ◽

10.4028/3-908451-06-x.345 ◽

2005 ◽

pp. 345-348

Author(s):

Han Xu ◽

Amy Shen ◽

Vlad Tarasov ◽

Brian White ◽

Josh Wolf

Keyword(s):

Cu Interconnect ◽

Low K

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Development of Voltammetry Techniques for Characterization of Porous Low-k/Cu Interconnect Integration Reliability

ECS Meeting Abstracts ◽

10.1149/ma2011-01/22/1410 ◽

2011 ◽

Keyword(s):

Cu Interconnect ◽

Low K

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Quantitative projections of reliability and performance for low-k/Cu interconnect systems

2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059) ◽

10.1109/relphy.2000.843939 ◽

2002 ◽

Cited By ~ 3

Author(s):

K. Banerjee ◽

A. Mehrotra ◽

W. Hunter ◽

K.C. Saraswat ◽

K.E. Goodson ◽

...

Keyword(s):

And Performance ◽

Cu Interconnect ◽

Interconnect Systems ◽

Low K

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A scalable low-k/Cu interconnect technology using i self-assembled ultra-low-k porous silica films

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. ◽

10.1109/icsict.2004.1435055 ◽

2005 ◽

Author(s):

T. Kikkawa ◽

Y. Oku ◽

K. Kohmura ◽

N. Fujii ◽

H. Tanaka ◽

...

Keyword(s):

Porous Silica ◽

Silica Films ◽

Self Assembled ◽

Cu Interconnect ◽

Interconnect Technology ◽

Low K

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Micromachined high-Q inductors in 0.18 μm Cu interconnect low-K CMOS

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) ◽

10.1109/cicc.2001.929846 ◽

2002 ◽

Cited By ~ 4

Author(s):

H. Lakdawala ◽

X. Zhu ◽

H. Luo ◽

S. Santhanam ◽

L.R. Carley ◽

...

Keyword(s):

High Q ◽

Cu Interconnect ◽

Low K

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TiN Metal Hardmask Residue Removal Formulation Development for Advanced Porous Low-K and Cu Interconnect Application

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.219.217 ◽

2014 ◽

Vol 219 ◽

pp. 217-220 ◽

Cited By ~ 1

Author(s):

Hua Cui

Keyword(s):

Aspect Ratio ◽

Metal Deposition ◽

Formulation Development ◽

Chemical Cleaning ◽

Residue Removal ◽

Profile Control ◽

Cu Interconnect ◽

Tin Metal ◽

Technology Nodes ◽

Low K

TiN metal hardmask has been used to improve etch selectivity to low-k materials and thereby gain better profile control. For 14 nm and smaller technology nodes, it is required that the TiN hardmask is completely removed in order to improve the aspect ratio for subsequent reliable metal deposition. Thus, a chemical cleaning formulation with high TiN etch selectivity toward Cu and low-k is required.

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Highly stable partial body tied SOI CMOS technology with Cu interconnect and low-k dielectric for high performance microprocessor

IEEE International SOI Conference SOI-02 ◽

10.1109/soi.2002.1044443 ◽

2002 ◽

Cited By ~ 1

Author(s):

Kim ◽

Oh ◽

Kang ◽

Oh ◽

Yoo ◽

...

Keyword(s):

High Performance ◽

Cmos Technology ◽

Partial Body ◽

Cu Interconnect ◽

Low K ◽

Soi Cmos

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S-parameters-based high speed signal characterization of Al and Cu interconnect on low-k hydrogen silsesquioxane-Si substrate

2007 International Microsystems, Packaging, Assembly and Circuits Technology ◽

10.1109/impact.2007.4433613 ◽

2007 ◽

Author(s):

Chia-Cheng Ho ◽

Bi-Shiou Chiou

Keyword(s):

High Speed ◽

Hydrogen Silsesquioxane ◽

Si Substrate ◽

S Parameters ◽

Cu Interconnect ◽

Signal Characterization ◽

Low K

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PECVD low-k SiOC (k=2.8) as a cap layer for 200nm pitch Cu interconnect using porous low-k dielectrics (k=2.3)

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) ◽

10.1109/iitc.2004.1345685 ◽

2004 ◽

Cited By ~ 3

Author(s):

S.G. Lee ◽

T. Yoshie ◽

Y. Sudo ◽

E. Soda ◽

K. Yoneda ◽

...

Keyword(s):

Cap Layer ◽

Cu Interconnect ◽

Low K

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A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

IEEE International Electron Devices Meeting 2003 ◽

10.1109/iedm.2003.1269411 ◽

2004 ◽

Cited By ~ 2

Author(s):

M. Tada ◽

Y. Harada ◽

T. Tamura ◽

N. Inoue ◽

F. Ito ◽

...

Keyword(s):

Cu Interconnect ◽

Interconnect Technology ◽

Low K

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