Low power circuit techniques for optimizing power in high speed SRAMs

2016 ◽  
Author(s):  
Navneet Kaur Saini ◽  
Aniruddha Gupta ◽  
Ravija Prashar ◽  
Parul Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Power Circuit ◽  
Circuit Techniques

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

Seek-method based 2’s complement circuit for low power circuit and high-speed operation

2021 ◽  
Author(s):  
S. Deepak ◽  
Ganesan. SaiKrishnan ◽  
D. Rajesh ◽  
J. V. R. Ravindra
Keyword(s):  
Low Power ◽  
High Speed ◽  
Power Circuit

Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes

2010 ◽  
Author(s):  
Yoonmyung Lee ◽  
Gregory Chen ◽  
Scott Hanson ◽  
Dennis Sylvester ◽  
David Blaauw
Keyword(s):  
Low Power ◽  
Sensor Nodes ◽  
Power Circuit ◽  
Ultra Low Power ◽  
New Class ◽  
Circuit Techniques

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

2011 ◽  
Vol 42 (12) ◽  
pp. 1343-1352 ◽  
Author(s):  
P. Saha ◽  
A. Banerjee ◽  
A. Dandapat ◽  
P. Bhattacharyya
Keyword(s):  
Low Power ◽  
High Speed ◽  
Power Circuit ◽  
Vedic Mathematics ◽  
Asic Design
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