scholarly journals Runtime and quality tradeoffs in FPGA placement and routing

2001 ◽  
Author(s):  
Chandra Mulpuri ◽  
Scott Hauck
Keyword(s):  
Fpga Placement ◽  
Placement And Routing

A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal

2015 ◽  
Vol 8 (2) ◽  
pp. 1-16
Author(s):  
Ricardo Ferreira ◽  
Luciana Rocha ◽  
André G. Santos ◽  
José A. M. Nacif ◽  
Stephan Wong ◽  
...  
Keyword(s):  
Low Complexity ◽  
Graph Traversal ◽  
Fpga Placement ◽  
Placement And Routing

scholarly journals Speeding Up FPGA Placement via Partitioning and Multithreading

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Cristinel Ababei
Keyword(s):  
Routing Algorithms ◽  
Design Flow ◽  
Wire Length ◽  
Fpga Design ◽  
Circuit Delay ◽  
Hybrid Parallelization ◽  
Multiple Cores ◽  
Fpga Placement ◽  
Placement And Routing ◽  
Placement Algorithm

One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of2.5×using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

2008 ◽  
Vol 43 (7) ◽  
pp. 151-160 ◽  
Author(s):  
Bjorn De Sutter ◽  
Paul Coene ◽  
Tom Vander Aa ◽  
Bingfeng Mei
Keyword(s):  
Register Allocation ◽  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Placement And Routing

Pathfinder Algorithm Modification for CPLD and FPGA Routing Stage

2021 ◽  
Vol 26 (5) ◽  
pp. 399-409
Author(s):  
M.A. Zapletina ◽  
◽  
S.V. Gavrilov ◽  
◽  
Keyword(s):  
Computer Aided Design ◽  
Digital Circuits ◽  
Routing Algorithm ◽  
Design Flow ◽  
Negative Effect ◽  
Industrial Projects ◽  
Placement And Routing ◽  
Aided Design ◽  
The Impact

One of the main advantages of FPGA and CPLD is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA/CPLD design flow. The quality of results of these stages is crucial to the final perfor-mance of custom digital circuits implemented on FPGA/CPLD. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA/CPLD by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resource graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. For experiments, the sets of test digital circuits ISCAS'85, ISCAS'89, LGSynth'89 and several custom industrial projects were used. The impact of the proposed algorithmic improvements was analyzed using four FPGA/CPLD architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA/CPLD architecture, with no significant negative effect on the timing characteristics of the designed circuits.

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