A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal

2015 ◽  
Vol 8 (2) ◽  
pp. 1-16
Author(s):  
Ricardo Ferreira ◽  
Luciana Rocha ◽  
André G. Santos ◽  
José A. M. Nacif ◽  
Stephan Wong ◽  
...  
Keyword(s):  
Low Complexity ◽  
Graph Traversal ◽  
Fpga Placement ◽  
Placement And Routing

scholarly journals Speeding Up FPGA Placement via Partitioning and Multithreading

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Cristinel Ababei
Keyword(s):  
Routing Algorithms ◽  
Design Flow ◽  
Wire Length ◽  
Fpga Design ◽  
Circuit Delay ◽  
Hybrid Parallelization ◽  
Multiple Cores ◽  
Fpga Placement ◽  
Placement And Routing ◽  
Placement Algorithm

One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of2.5×using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

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