A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits

2021 ◽  
Vol 26 (6) ◽  
pp. 1-17
Author(s):  
Xi Li ◽  
Soheil Nazar Shahsavani ◽  
Xuan Zhou ◽  
Massoud Pedram ◽  
Peter A. Beerel
Keyword(s):  
Hold Time ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuits ◽  
Oxide Semiconductor ◽  
Flux Quantum ◽  
Common Path ◽  
Incremental Placement ◽  
Layout Area ◽  
Eda Tools

Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

scholarly journals Fault Modeling of Graphene Nanoribbon FET Logic Circuits

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 851 ◽  
Author(s):  
Gil-Tomàs ◽  
Gracia-Morán ◽  
Saiz-Adalid ◽  
Gil-Vicente
Keyword(s):  
Field Effect Transistor ◽  
Fault Tolerant ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Graphene Nanoribbon ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fault Models ◽  
New Materials ◽  
Effect Transistor

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

scholarly journals Prediction of a Two-Transistor Vertical QNOT Gate

2020 ◽  
Vol 10 (21) ◽  
pp. 7597
Author(s):  
Heesung Han ◽  
Chang-Hyun Kim
Keyword(s):  
Finite Element ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
Material Parameters ◽  
Element Simulation ◽  
Charge Injection Barrier ◽  
Injection Barrier

A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550008 ◽  
Author(s):  
Bander Saman ◽  
P. Mirdha ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. C. Jain ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Proposed Model ◽  
High Band

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

Electromechanical Computing at 500°C with Silicon Carbide

Science ◽  
2010 ◽  
Vol 329 (5997) ◽  
pp. 1316-1318 ◽  
Author(s):  
Te-Hao Lee ◽  
Swarup Bhunia ◽  
Mehran Mehregany
Keyword(s):  
Silicon Carbide ◽  
Thermal Management ◽  
High Performance ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Propulsion Systems ◽  
Heat Sinking

Logic circuits capable of operating at high temperatures can alleviate expensive heat-sinking and thermal-management requirements of modern electronics and are enabling for advanced propulsion systems. Replacing existing complementary metal-oxide semiconductor field-effect transistors with silicon carbide (SiC) nanoelectromechanical system (NEMS) switches is a promising approach for low-power, high-performance logic operation at temperatures higher than 300°C, beyond the capability of conventional silicon technology. These switches are capable of achieving virtually zero off-state current, microwave operating frequencies, radiation hardness, and nanoscale dimensions. Here, we report a microfabricated electromechanical inverter with SiC complementary NEMS switches capable of operating at 500°C with ultralow leakage current.

scholarly journals An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

2021 ◽  
Author(s):  
Muhammad Farhan Azmine ◽  
Urmi Debnath ◽  
Yeasir Arafat
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Building Blocks ◽  
Oxide Semiconductor ◽  
Memory Element ◽  
Area Efficiency ◽  
Arithmetic Logic Unit ◽  
Non Volatile Memory ◽  
Electrical Component ◽  
Logic Unit

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

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