Hardware Trojan Horse Detection through Improved Switching of Dormant Nets

2021 ◽  
Vol 17 (3) ◽  
pp. 1-22
Author(s):  
Tapobrata Dhar ◽  
Surajit Kumar Roy ◽  
Chandan Giri
Keyword(s):  
Integrated Circuits ◽  
Manufacturing Process ◽  
Test Phase ◽  
Side Channel ◽  
Hardware Trojan ◽  
Side Channel Analysis ◽  
Area Overhead ◽  
Channel Analysis ◽  
Testability Measures ◽  
Simulation Results

Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC considering various circuit parameters and testability measures to bolster the transitions in logic values of the nets throughout the IC while minimising the area overhead. Simulation results show a significant increase in transitions in logic values within HTH triggers using this method, thus aiding in their detection through side-channel analysis or direct activation of the payload.

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection

2017 ◽  
Author(s):  
Fakir Sharif Hossain ◽  
Tomokazu Yoneda ◽  
Michihiro Shintani ◽  
Michiko Inoue ◽  
Alex Orailoglo
Keyword(s):  
Side Channel ◽  
Hardware Trojan ◽  
Side Channel Analysis ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Channel Analysis

scholarly journals Spin Me Right Round Rotational Symmetry for FPGA-Specific AES

2018 ◽  
pp. 596-626 ◽  
Author(s):  
Lauren De Meyer ◽  
Amir Moradi ◽  
Felix Wegener
Keyword(s):  
Integrated Circuits ◽  
Rotational Symmetry ◽  
Side Channel ◽  
Side Channel Analysis ◽  
Trade Offs ◽  
The Status ◽  
Field Programmable ◽  
New Construction ◽  
Channel Analysis ◽  
The Cost

The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naïve implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

A Side-Channel Analysis for Hardware Trojan Detection Based on Path Delay Measurement

2018 ◽  
Vol 27 (09) ◽  
pp. 1850138 ◽  
Author(s):  
Atieh Amelian ◽  
Shahram Etemadi Borujeni
Keyword(s):  
Integrated Circuit ◽  
Side Channel ◽  
Hardware Trojan ◽  
Path Delay ◽  
Side Channel Analysis ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Delay Measurement ◽  
Channel Analysis ◽  
Circuit Function

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01[Formula: see text]ns can detect more than 80% of Trojans.

Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis

2016 ◽  
Vol 6 (3) ◽  
pp. 239-247 ◽  
Author(s):  
Xuan Thuy Ngo ◽  
Zakaria Najm ◽  
Shivam Bhasin ◽  
Sylvain Guilley ◽  
Jean-Luc Danger
Keyword(s):  
Trojan Horse ◽  
Side Channel ◽  
Hardware Trojan ◽  
Side Channel Analysis ◽  
Channel Analysis ◽  
Process Dispersion

A Method of Detecting Hardware Trojans Based on Side-Channel Analysis

2014 ◽  
Vol 536-537 ◽  
pp. 558-561
Author(s):  
Wen Feng Feng ◽  
Lei Li ◽  
Zhen Li
Keyword(s):  
Integrated Circuits ◽  
Detection Methods ◽  
Side Channel ◽  
Process Noise ◽  
Hardware Trojans ◽  
Side Channel Analysis ◽  
Benchmark Circuit ◽  
Design And Manufacturing ◽  
Channel Analysis ◽  
Power Delay Product

In recent years, integrated circuits subject to hardware Trojans attack in the design and manufacturing process, the security of chip and hardware security was threatened. Some detection methods of have been proposed, the most common of those methods is based on side-channel signal analysis, however, since the effect of process noise, considering only the unilateral information that is difficult to effectively distinguish the noise and Trojans circuit. In this paper, the method still based on side-channel signal, but it is a combination of power and delay which was called the power-delay product (PDP). The idea proposed is verified by the benchmark circuit iscas85, the experimental results show that this method can effectively improve detection probability.

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