Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

P. Veda Bhanu; Pranav Venkatesh Kulkarni; Soumya J

doi:10.1145/3269983

Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

ACM Journal on Emerging Technologies in Computing Systems ◽

10.1145/3269983 ◽

2019 ◽

Vol 15 (1) ◽

pp. 1-23 ◽

Cited By ~ 1

Author(s):

P. Veda Bhanu ◽

Pranav Venkatesh Kulkarni ◽

Soumya J

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

On Chip

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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081674 ◽

2011 ◽

Author(s):

Zhiliang Qian ◽

Ying Fei Teh ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

Chip Design ◽

On Chip

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Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-32-9767-8_37 ◽

2019 ◽

pp. 442-454

Author(s):

P. Veda Bhanu ◽

Pranav V. Kulkarni ◽

Sai Pranavi Avadhanam ◽

J. Soumya ◽

Linga Reddy Cenkeramaddi

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Reconfigurable Architecture ◽

Chip Design ◽

Mesh Topology ◽

On Chip

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Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization

2019 14th Conference on Industrial and Information Systems (ICIIS) ◽

10.1109/iciis47346.2019.9063339 ◽

2019 ◽

Author(s):

P. Veda Bhanu ◽

J. Soumya

Keyword(s):

Particle Swarm Optimization ◽

Fault Tolerant ◽

Particle Swarm ◽

Network On Chip ◽

Discrete Particle Swarm Optimization ◽

Chip Design ◽

Swarm Optimization ◽

Discrete Particle ◽

On Chip ◽

Application Specific

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Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 ◽

10.1145/1366110.1366184 ◽

2008 ◽

Author(s):

Xianfang Tan ◽

Lei Zhang ◽

Shankar Neelkrishnan ◽

Mei Yang ◽

Yingtao Jiang ◽

...

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

On Chip

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Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization

TENCON 2018 - 2018 IEEE Region 10 Conference ◽

10.1109/tencon.2018.8650346 ◽

2018 ◽

Author(s):

P. Veda Bhanu ◽

Pranav Kulkarni ◽

Sarthak Jain ◽

Soumya J ◽

Linga Reddy Cenkarmaddi ◽

...

Keyword(s):

Particle Swarm Optimization ◽

Fault Tolerant ◽

Particle Swarm ◽

Network On Chip ◽

Tree Topology ◽

Chip Design ◽

Swarm Optimization ◽

On Chip

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Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) ◽

10.1109/prime.2018.8430343 ◽

2018 ◽

Author(s):

P. Veda Bhanu ◽

Pranav Kulkarni ◽

Soumya J. ◽

Linga Reddy Cenkarmaddi ◽

Henning Idsoe

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

On Chip

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Butterfly-Fat-Tree Topology-Based Fault-Tolerant Network-on-Chip Design Using Particle Swarm Optimization

Harmony Search and Nature Inspired Optimization Algorithms - Advances in Intelligent Systems and Computing ◽

10.1007/978-981-13-0761-4_108 ◽

2018 ◽

pp. 1165-1175

Author(s):

P. Veda Bhanu ◽

Pranav Venkatesh Kulkarni ◽

U. Anil Kumar ◽

J. Soumya

Keyword(s):

Particle Swarm Optimization ◽

Fault Tolerant ◽

Particle Swarm ◽

Network On Chip ◽

Tree Topology ◽

Chip Design ◽

Swarm Optimization ◽

On Chip

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Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation

Journal of Experimental & Theoretical Artificial Intelligence ◽

10.1080/0952813x.2019.1597174 ◽

2019 ◽

Vol 31 (5) ◽

pp. 781-799

Author(s):

P. Veda Bhanu ◽

Pranav Venkatesh Kulkarni ◽

Soumya J

Keyword(s):

Fault Tolerant ◽

Particle Swarm ◽

Network On Chip ◽

Particle Swarm Optimisation ◽

Tree Topology ◽

Chip Design ◽

On Chip

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High-performance, energy-efficient, fault-tolerant network-on-chip design using reinforcement learning

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.23919/date.2019.8714869 ◽

2019 ◽

Cited By ~ 7

Author(s):

Ke Wang ◽

Ahmed Louri ◽

Avinash Karanth ◽

Razvan Bunescu

Keyword(s):

Reinforcement Learning ◽

Energy Efficient ◽

High Performance ◽

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

On Chip

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A strategy for fault tolerant reconfigurable Network-on-Chip design

2016 20th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/isvdat.2016.8064893 ◽

2016 ◽

Cited By ~ 1

Author(s):

Navonil Chatterjee ◽

Priyajit Mukherjee ◽

Santanu Chattopadhyay

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

On Chip

Download Full-text