High-performance, energy-efficient, fault-tolerant network-on-chip design using reinforcement learning

2019 ◽  
Author(s):  
Ke Wang ◽  
Ahmed Louri ◽  
Avinash Karanth ◽  
Razvan Bunescu
Keyword(s):  
Reinforcement Learning ◽  
Energy Efficient ◽  
High Performance ◽  
Fault Tolerant ◽  
Network On Chip ◽  
Chip Design ◽  
On Chip

High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics

2016 ◽  
Vol 15 (4) ◽  
pp. 1-26 ◽  
Author(s):  
Karthi Duraisamy ◽  
Hao Lu ◽  
Partha Pratim Pande ◽  
Ananth Kalyanaraman
Keyword(s):  
Energy Efficient ◽  
High Performance ◽  
Network On Chip ◽  
Graph Analytics ◽  
On Chip

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

2019 ◽  
Vol 15 (1) ◽  
pp. 1-23 ◽  
Author(s):  
P. Veda Bhanu ◽  
Pranav Venkatesh Kulkarni ◽  
Soumya J
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Chip Design ◽  
On Chip
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