scholarly journals An Alternative TAGE-like Conditional Branch Predictor

2018 ◽  
Vol 15 (3) ◽  
pp. 1-23 ◽  
Author(s):  
Pierre Michaud
Keyword(s):  
Branch Predictor ◽  
Conditional Branch

Design tradeoffs for the Alpha EV8 conditional branch predictor

2002 ◽  
Vol 30 (2) ◽  
pp. 295-306 ◽  
Author(s):  
André Seznec ◽  
Stephen Felix ◽  
Venkata Krishnan ◽  
Yiannakis Sazeides
Keyword(s):  
Branch Predictor ◽  
Design Tradeoffs ◽  
Conditional Branch

Towards the Improving Branch Instructions Identification in High- Performance Processors: Issues, Challenges and Techniques

2021 ◽  
Vol 14 ◽  
Author(s):  
Sweety Nain ◽  
Prachi Chaudhary
Keyword(s):  
Continuous Flow ◽  
High Performance ◽  
Branch Prediction ◽  
Parallel Processors ◽  
Processor Performance ◽  
Branch Predictor ◽  
Prediction Technique ◽  
Execution Speed ◽  
Conditional Branch

Introduction: Accurate branch prediction technique has become compulsory in the superscalar and deep pipeline processors. The conditional instructions can break the continuous flow of execution in the pipeline stages, thereby decreasing processor performance. Discussion: This paper highlights the concept of branch prediction, some issues and challenges, and techniques for improving processor performance. Further, this paper also presents the role of branch prediction in different processors and their features. Conclusion: The concept of the branch prediction used in parallel processors to enhance the execution speed of the conditional branch instructions and improve the processor's performance is highlighted in this paper. Further, this paper highlights the branch predictor techniques with their features and presents the challenges, issues, and future techniques related to the branch prediction.

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

2014 ◽  
Vol 72 (5) ◽  
pp. 1679-1693 ◽  
Author(s):  
Cong Thuan Do ◽  
Hong Jun Choi ◽  
Dong Oh Son ◽  
Jong Myon Kim ◽  
Cheol Hong Kim
Keyword(s):  
High Performance ◽  
Embedded Processors ◽  
Branch Predictor

Simulation and Implementation of HLA-Based Branch Predictor of Multi-Pipeline Processor

2012 ◽  
Vol 204-208 ◽  
pp. 4952-4957
Author(s):  
Ji Hua Ye ◽  
Qi Xie ◽  
Yao Hong Xiahou
Keyword(s):  
Simulation System ◽  
New Method ◽  
High Level Architecture ◽  
Hit Rate ◽  
Branch Predictor ◽  
The Right ◽  
High Level ◽  
Two Sides

Researched how the multi-pipeline processor accelerates the running of thread ,found that when the branch predictor facing the random branch instruction, the hit rate will become very low, so bring out a new method that using the free pipeline to accelerate the running of branch instruction. If the right prediction from branch predictor is less than 70% and there is a free pipeline, then using two pipelines to run the two sides of a branch instruction at the same time. In order to test the new method, the HLA (High Level architecture) architecture-based simulation system is established, the results show that the new method can really reduce the time when processing the random branch instructions.

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