Low power synthesis of dual threshold voltage CMOS VLSI circuits

1999 ◽  
Author(s):  
Vijay Sundararajan ◽  
Keshab K. Parhi
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Vlsi Circuits ◽  
Dual Threshold Voltage ◽  
Cmos Vlsi ◽  
Low Power Synthesis

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

2018 ◽  
Vol 37 (3) ◽  
pp. 1189-1203
Author(s):  
Behnam Ghavami
Keyword(s):  
Low Power ◽  
Spatial Correlation ◽  
Threshold Voltage ◽  
High Performance ◽  
Process Variations ◽  
Low Power Design ◽  
Asynchronous Circuits ◽  
Asynchronous Circuit ◽  
Content Type ◽  
Dual Threshold Voltage

Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

scholarly journals Design of Low Power Digital Multiplier Using Dual Threshold Voltage Adder Module

2012 ◽  
Vol 30 ◽  
pp. 1179-1186 ◽  
Author(s):  
L. Raja ◽  
B.M. Prabhu ◽  
K. Thanushkodi
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Dual Threshold Voltage

scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

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