A cost-effective, high-bandwidth storage architecture

1998 ◽  
Author(s):  
Garth A. Gibson ◽  
Jim Zelenka ◽  
David F. Nagle ◽  
Khalil Amiri ◽  
Jeff Butler ◽  
...  
Keyword(s):  
Cost Effective ◽  
High Bandwidth

scholarly journals An Introduction to 5G Network Slicing Technology

Telecom IT ◽  
2019 ◽  
Vol 7 (4) ◽  
pp. 21-29
Author(s):  
B. Goldstein ◽  
V. Elagin ◽  
K. Kobzev ◽  
A. Grebenshchikova
Keyword(s):  
Service Providers ◽  
Smart Cities ◽  
Effective Means ◽  
Cost Effective ◽  
Network Slicing ◽  
Radio Access ◽  
5G Network ◽  
High Bandwidth ◽  
Shared Infrastructure ◽  
Levels Of Service

Communications Service Providers are looking to 5G technology as an enabler for new revenues, with network slicing providing a cost-effective means of supporting multiple services on shared infrastructure. Different radio access technologies, network architectures, and core functions can be brought together under software control to deliver appropriate Quality of Service “slices,” enabling new levels of service innovation, such as high bandwidth for video applications, low latency for automation, and mass connectivity for Smart Cities.

Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board

2018 ◽  
Vol 2018 (1) ◽  
pp. 000384-000388
Author(s):  
Brian Curran ◽  
Jacob Reyes ◽  
Christian Tschoban ◽  
Ivan Ndip ◽  
Klaus-Dieter Lang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Antenna Arrays ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Front End ◽  
High Bandwidth ◽  
Increasing Demand ◽  
K Band

Abstract Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.

Angara interconnect makes GPU-based Desmos supercomputer an efficient tool for molecular dynamics calculations

2019 ◽  
Vol 33 (3) ◽  
pp. 507-521 ◽  
Author(s):  
Vladimir Stegailov ◽  
Ekaterina Dlinnova ◽  
Timur Ismagilov ◽  
Mikhail Khalilov ◽  
Nikolay Kondratyuk ◽  
...  
Keyword(s):  
Molecular Dynamics ◽  
Message Passing ◽  
High Performance ◽  
Message Passing Interface ◽  
Job Scheduling ◽  
Cost Effective ◽  
Test Bed ◽  
Molecular Dynamics Calculations ◽  
High Bandwidth ◽  
Network Topologies

In this article, we describe the Desmos supercomputer that consists of 32 hybrid nodes connected by a low-latency high-bandwidth Angara interconnect with torus topology. This supercomputer is aimed at cost-effective classical molecular dynamics calculations. Desmos serves as a test bed for the Angara interconnect that supports 3-D and 4-D torus network topologies and verifies its ability to unite massively parallel programming systems speeding-up effectively message-passing interface (MPI)-based applications. We describe the Angara interconnect presenting typical MPI benchmarks. Desmos benchmarks results for GROMACS, LAMMPS, VASP and CP2K are compared with the data for other high-performance computing (HPC) systems. Also, we consider the job scheduling statistics for several months of Desmos deployment.

scholarly journals Discrete-variable quantum key distribution with homodyne detection

Quantum ◽  
2022 ◽  
Vol 6 ◽  
pp. 613
Author(s):  
Ignatius William Primaatmaja ◽  
Cassey Crystania Liang ◽  
Gong Zhang ◽  
Jing Yan Haw ◽  
Chao Wang ◽  
...  
Keyword(s):  
Quantum Key Distribution ◽  
High Speed ◽  
Cost Effective ◽  
Key Distribution ◽  
Continuous Variable ◽  
Discrete Variable ◽  
Quantum State Preparation ◽  
High Bandwidth ◽  
The Cost ◽  
Selection Of

Most quantum key distribution (QKD) protocols can be classified as either a discrete-variable (DV) protocol or continuous-variable (CV) protocol, based on how classical information is being encoded. We propose a protocol that combines the best of both worlds – the simplicity of quantum state preparation in DV-QKD together with the cost-effective and high-bandwidth of homodyne detectors used in CV-QKD. Our proposed protocol has two highly practical features: (1) it does not require the honest parties to share the same reference phase (as required in CV-QKD) and (2) the selection of decoding basis can be performed after measurement. We also prove the security of the proposed protocol in the asymptotic limit under the assumption of collective attacks. Our simulation suggests that the protocol is suitable for secure and high-speed practical key distribution over metropolitan distances.

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000930-000959
Author(s):  
Wael Zohni ◽  
Rajesh Katkar ◽  
Rey Co ◽  
Rizza Cizek
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Volume ◽  
Third Party ◽  
High Yield ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Manufacturing Readiness

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

Leveraging NVMe SSDs for Building a Fast, Cost-effective, LSM-tree-based KV Store

2021 ◽  
Vol 17 (4) ◽  
pp. 1-29
Author(s):  
Cheng Li ◽  
Hao Chen ◽  
Chaoyi Ruan ◽  
Xiaosong Ma ◽  
Yinlong Xu
Keyword(s):  
High Speed ◽  
Scale Up ◽  
Cost Effective ◽  
Data Migration ◽  
Solid State Drives ◽  
Content Type ◽  
Memory Processing ◽  
Recent Emergence ◽  
Non Volatile Memory ◽  
High Bandwidth

Key-value (KV) stores support many crucial applications and services. They perform fast in-memory processing but are still often limited by I/O performance. The recent emergence of high-speed commodity non-volatile memory express solid-state drives (NVMe SSDs) has propelled new KV system designs that take advantage of their ultra-low latency and high bandwidth. Meanwhile, to switch to entirely new data layouts and scale up entire databases to high-end SSDs requires considerable investment. As a compromise, we propose SpanDB, an LSM-tree-based KV store that adapts the popular RocksDB system to utilize selective deployment of high-speed SSDs . SpanDB allows users to host the bulk of their data on cheaper and larger SSDs (and even hard disc drives with certain workloads), while relocating write-ahead logs (WAL) and the top levels of the LSM-tree to a much smaller and faster NVMe SSD. To better utilize this fast disk, SpanDB provides high-speed, parallel WAL writes via SPDK, and enables asynchronous request processing to mitigate inter-thread synchronization overhead and work efficiently with polling-based I/O. To ease the live data migration between fast and slow disks, we introduce TopFS, a stripped-down file system providing familiar file interface wrappers on top of SPDK I/O. Our evaluation shows that SpanDB simultaneously improves RocksDB's throughput by up to 8.8 \times and reduces its latency by 9.5–58.3%. Compared with KVell, a system designed for high-end SSDs, SpanDB achieves 96–140% of its throughput, with a 2.3–21.6 \times lower latency, at a cheaper storage configuration.

scholarly journals Exploring Attack vectors and Security Challenges in SDN

2019 ◽  
Vol 8 (11) ◽  
pp. 2945-2949
Keyword(s):  
Network Security ◽  
Software Defined Networking ◽  
Cost Effective ◽  
Emerging Technology ◽  
Centralized Control ◽  
Security Issues ◽  
Important Concern ◽  
Security Challenges ◽  
High Bandwidth ◽  
Multiple Devices

Software Defined Networking (SDN) is a modern emerging technology in networking. SDN desires to furnish with composite and exclusive networking sources, it needs to decouple of carrier plane and the control plane, and also provides centralized control. The benefits of network programmability, dynamic computing, cost effective, high bandwidth, of SDN applications are discussed, but security has become an important concern. While centralized controller controlling multiple devices, this change in traditional network will be the main impact on network security. In this paper, we discuss about security issues and challenges in SDN architecture planes.

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