Synchronization for a multi-port frame buffer on a mesh-connected multicomputer

1995 ◽  
Author(s):  
Bin Wei ◽  
Gordon Stoll ◽  
Douglas W. Clark ◽  
Edward W. Felten ◽  
Kai Li ◽  
...  
Keyword(s):  
Frame Buffer

scholarly journals An Effective Burst Access Scheme for Lossless Frame Buffer Compression on a Video Decoder

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 124419-124424
Author(s):  
Jaeshin Lee ◽  
Imjae Hwang ◽  
Youngsik Kim ◽  
Cheong Ghil Kim ◽  
Woo-Chan Park
Keyword(s):  
Video Decoder ◽  
Frame Buffer ◽  
Access Scheme

A frame buffer system with enhanced functionality

1981 ◽  
Vol 15 (3) ◽  
pp. 63-69 ◽  
Author(s):  
F. C. Crow ◽  
M. W. Howard
Keyword(s):  
Buffer System ◽  
Frame Buffer

28-nm 0.08 mm2/Mb Embedded MRAM for Frame Buffer Memory

2020 ◽  
Author(s):  
S. H. Han ◽  
J. M. Lee ◽  
H. M. Shin ◽  
J. H. Lee ◽  
K. S. Suh ◽  
...  
Keyword(s):  
Buffer Memory ◽  
Frame Buffer ◽  
28 Nm

D-buffer: irregular image data storage made practical

2013 ◽  
Vol 21 (1) ◽  
Author(s):  
J. Lipowski
Keyword(s):  
Data Storage ◽  
Image Data ◽  
Development Aid ◽  
Graphics Hardware ◽  
Address Space ◽  
Output Data ◽  
Frame Buffer ◽  
New Methods ◽  
Hardware Architectures ◽  
Depth Buffer

AbstractModern hardware accelerated graphics pipelines are designed to operate on data in a so called streaming model. To process the data in this model one needs to impose some restrictions on input and output argument’s (most frequently represented by a two-dimensional frame buffer) memory structure. The output data regularity is obvious when we consider rasterizing hardware architecture, which draws 3D polygons using depth buffer to resolve the visible surface problem. But recently the user’s needs surpass those restrictions with increasing frequency. In this work we formulate and present new methods of irregular frame buffer storage and ordering. The so called deque buffer (or D-buffer) allows us to decrease the amount of memory used for storage as well as the memory latency cost by using pixel data ordering. Our findings are confirmed by experimental results that measure the processing time, which is up to four times shorter, when compared with previous work by other authors. We also include a detailed description of algorithms used for D-buffer construction on the last three consumer-grade graphics hardware architectures, as a guide for other researchers and a development aid for practitioners. The only theoretical requirement imposed by our method is the use of memory model with linear address space.

A 10 Mb frame buffer memory with Z-compare and A-blend units

1995 ◽  
Vol 30 (12) ◽  
pp. 1563-1568 ◽  
Author(s):  
K. Inoue ◽  
H. Nakamura ◽  
H. Kawai
Keyword(s):  
Buffer Memory ◽  
Frame Buffer

scholarly journals Real-time Frame Buffer Implementation based on External Memory using FPGA

2018 ◽  
Vol 131 ◽  
pp. 641-646
Author(s):  
Dogancan Davutoglu ◽  
Nerhun Yildiz ◽  
Umut Engin Ayten ◽  
Vedat Tavsanoglu
Keyword(s):  
Real Time ◽  
Time Frame ◽  
External Memory ◽  
Frame Buffer
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