A 10 Mb frame buffer memory with Z-compare and A-blend units

1995 ◽  
Vol 30 (12) ◽  
pp. 1563-1568 ◽  
Author(s):  
K. Inoue ◽  
H. Nakamura ◽  
H. Kawai
Keyword(s):  
Author(s):  
S. H. Han ◽  
J. M. Lee ◽  
H. M. Shin ◽  
J. H. Lee ◽  
K. S. Suh ◽  
...  
Keyword(s):  

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 124419-124424
Author(s):  
Jaeshin Lee ◽  
Imjae Hwang ◽  
Youngsik Kim ◽  
Cheong Ghil Kim ◽  
Woo-Chan Park

1981 ◽  
Vol 15 (3) ◽  
pp. 63-69 ◽  
Author(s):  
F. C. Crow ◽  
M. W. Howard
Keyword(s):  

2013 ◽  
Vol 21 (1) ◽  
Author(s):  
J. Lipowski

AbstractModern hardware accelerated graphics pipelines are designed to operate on data in a so called streaming model. To process the data in this model one needs to impose some restrictions on input and output argument’s (most frequently represented by a two-dimensional frame buffer) memory structure. The output data regularity is obvious when we consider rasterizing hardware architecture, which draws 3D polygons using depth buffer to resolve the visible surface problem. But recently the user’s needs surpass those restrictions with increasing frequency. In this work we formulate and present new methods of irregular frame buffer storage and ordering. The so called deque buffer (or D-buffer) allows us to decrease the amount of memory used for storage as well as the memory latency cost by using pixel data ordering. Our findings are confirmed by experimental results that measure the processing time, which is up to four times shorter, when compared with previous work by other authors. We also include a detailed description of algorithms used for D-buffer construction on the last three consumer-grade graphics hardware architectures, as a guide for other researchers and a development aid for practitioners. The only theoretical requirement imposed by our method is the use of memory model with linear address space.


Webology ◽  
2021 ◽  
Vol 18 (Special Issue 04) ◽  
pp. 1436-1448
Author(s):  
Jumana Suhail ◽  
Dr. Khalida Sh. Rijab

The paper proposes a methodology for estimating packet flowing at the sensor level in SDN-WSN based on the partial congestion controller with Kalman filter. Furthermore, the actual purpose of proposing such methodology for predicting in advance the subsequent step of packet flow, and that will consequently contribute in reducing the congestion that might happen. The model proposed (SDN with Kalman filter) is optimized using congestion controller, the methodology of proposed work, the first step random distributed of random node, the apply the Kmean cluster of select the head cluster node in, the connected the network based on LEACH protocol. in this work proposed SDN with Kalman filter for control on network and reduce error of data, where achieve by add buffer memory for each nodes and head cluster to store the data, and SDN control on transmit ion data and receiver data, before transmit apply the Kalman filter on data to reduce error data. The proposed technique, according to simulation findings, extends the network's lifetime by over 30% more than typical WSNs, the reduce the average density of memory to 20% than traditional WSN, and the increase the average capacity of memory to 20% than traditional WSN.


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