Double-edge-triggered D-flip-flops for high-speed CMOS circuits

1991 ◽  
Vol 26 (8) ◽  
pp. 1168-1170 ◽  
Author(s):  
M. Afghahi ◽  
J. Yuan
Keyword(s):  
High Speed ◽  
Cmos Circuits ◽  
Double Edge

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals A gate-delay model for high-speed CMOS circuits

1994 ◽  
Author(s):  
Florentin Dartu ◽  
Noel Menezes ◽  
Jessica Qian ◽  
Lawrence T. Pillage
Keyword(s):  
High Speed ◽  
Cmos Circuits ◽  
Gate Delay ◽  
Delay Model

Ultra-high speed CMOS circuits in thin SIMOX films

2003 ◽  
Author(s):  
A. Kamgar ◽  
S.J. Hillenius ◽  
H.-I. Cong ◽  
R.L. Field ◽  
W.S. Lindenberger ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Circuits ◽  
Ultra High Speed

Organic Pseudo-CMOS Circuits for Low-Voltage Large-Gain High-Speed Operation

2011 ◽  
Vol 32 (10) ◽  
pp. 1448-1450 ◽  
Author(s):  
Kenjiro Fukuda ◽  
Tsuyoshi Sekitani ◽  
Tomoyuki Yokota ◽  
Kazunori Kuribara ◽  
Tsung-Ching Huang ◽  
...  
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Cmos Circuits ◽  
Large Gain

The Design of High Speed LVDS Parallel Port Communication Protocol

2015 ◽  
Vol 740 ◽  
pp. 852-856
Author(s):  
Lei Zheng ◽  
Chen Xi Yang ◽  
Jia Kang Liu
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Gigabit Ethernet ◽  
System A ◽  
Double Edge ◽  
Differential Signaling ◽  
Point To Point ◽  
Edge Sampling ◽  
Electrical Connections ◽  
And Control

In the image display and control system, a high speed dissymmetrical point to point communication port and protocol between GENIC(Gigabit Ethernet Network Interface Card) and SDRAM based on LVDS (Low Voltage Differential signaling) and STOP-WAIT ARQ protocol are designed, while the port’s speed should not below 1Gbps. Five lines LVDS signal pairs are used in one direction, including one clock and four data in the port’s electrical connections. Double-edge sampling and source synchronizing are also used. Mode 256 checkout is used to guarantee the reliable data transmission. Analysis shows that the port’s bandwidth is 1.2Gbps, the efficiency of protocol is above 99% and the protocol works steadily and reliably.

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