Description and Applications of a CMOS Digital Vision Chip Using General Purpose Processing Elements

2001 ◽  
Author(s):  
Masatoshi Ishikawa
Keyword(s):  
General Purpose ◽  
Vision Chip ◽  
Processing Elements

Device and System Development of General Purpose Digital Vision Chip

2000 ◽  
Vol 12 (5) ◽  
pp. 515-520 ◽  
Author(s):  
Takashi Komuro ◽  
◽  
Shingo Kagami ◽  
Idaku Ishii ◽  
Masatoshi Ishikawa
Keyword(s):  
Visual Feedback ◽  
High Speed ◽  
Robot Control ◽  
System Development ◽  
Vision System ◽  
General Purpose ◽  
Cmos Process ◽  
Vision Chip ◽  
Processing Elements ◽  
Photo Detectors

We have been developing a VLSI device called vision chip in which photo detectors are integrated with paralled processing elements and that realizes high speed robot control using visual feedback. Using a 0.35μm CMOS process, we have developed a 16 × 16 prototype chip and have demonstrated some image acquiring and processing experiments. A vision system which includes the vision chip has also been constructed.

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture

2000 ◽  
Vol 12 (5) ◽  
pp. 521-526
Author(s):  
Masanori Hariyama ◽  
◽  
Michitaka Kameyama
Keyword(s):  
Stereo Vision ◽  
Stereo Matching ◽  
Parallel Architecture ◽  
Window Size ◽  
Input Image ◽  
General Purpose ◽  
Image Size ◽  
Matching Algorithm ◽  
Processing Elements ◽  
General Purpose Processor

This article presents a stereo-matching algorithm to establish reliable correspondence between images by selecting a desirable window size for SAD (Sum of Absolute Differences) computation. In SAD computation, parallelism between pixels in a window changes depending on its window size, while parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is proposed to achieve 100% utilization of processing elements. Performance of the VLSI processor is evaluated to be more than 10,000 times higher than that of a general-purpose processor.

General-purpose vision chip architecture for real-time machine vision

1997 ◽  
Vol 12 (6) ◽  
pp. 619-627 ◽  
Author(s):  
Takashi Komuro ◽  
Idaku Ish ◽  
Masatoshi Ishikawa
Keyword(s):  
Machine Vision ◽  
Real Time ◽  
General Purpose ◽  
Time Machine ◽  
Vision Chip

scholarly journals A Manycore Vision Processor for Real-Time Smart Cameras

Sensors ◽  
2021 ◽  
Vol 21 (21) ◽  
pp. 7137
Author(s):  
Bruno A. da Silva ◽  
Arthur M. Lima ◽  
Janier Arias-Garcia ◽  
Michael Huebner ◽  
Jones Yudi
Keyword(s):  
Real Time ◽  
Distributed Processing ◽  
General Purpose ◽  
Frame Rate ◽  
Suitable Alternative ◽  
Smart Cameras ◽  
Real Time Processing ◽  
Processing Elements ◽  
General Purpose Processor ◽  
On Chip

Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Cameras for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed processing elements and memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to eighty-one processing elements were implemented and compared to several works from the literature. Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.

A Neural Net Associative Memory for Real-Time Applications

1990 ◽  
Vol 2 (1) ◽  
pp. 107-115 ◽  
Author(s):  
Gregory L. Heileman ◽  
George M. Papadourakis ◽  
Michael Georgiopoulos
Keyword(s):  
Neural Network ◽  
Real Time ◽  
Associative Memory ◽  
General Purpose ◽  
Hopfield Network ◽  
Neural Net ◽  
Single Chip ◽  
Processing Elements ◽  
Processing Times ◽  
Real Time Applications

A parallel hardware implementation of the associative memory neural network introduced by Hopfield is described. The design utilizes the Geometric Arithmetic Parallel Processor (GAPP), a commercially available single-chip VLSI general-purpose array processor consisting of 72 processing elements. The ability to cascade these chips allows large arrays of processors to be easily constructed and used to implement the Hopfield network. The memory requirements and processing times of such arrays are analyzed based on the number of nodes in the network and the number of exemplar patterns. Compared with other digital implementations, this design yields significant improvements in runtime performance and offers the capability of using large neural network associative memories in real-time applications.

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