Vision chip architecture using general-purpose processing elements for 1 ms vision system

2002 ◽  
Author(s):  
T. Komuro ◽  
I. Ishii ◽  
M. Ishikawa
Keyword(s):  
Vision System ◽  
General Purpose ◽  
Vision Chip ◽  
Processing Elements

Device and System Development of General Purpose Digital Vision Chip

2000 ◽  
Vol 12 (5) ◽  
pp. 515-520 ◽  
Author(s):  
Takashi Komuro ◽  
◽  
Shingo Kagami ◽  
Idaku Ishii ◽  
Masatoshi Ishikawa
Keyword(s):  
Visual Feedback ◽  
High Speed ◽  
Robot Control ◽  
System Development ◽  
Vision System ◽  
General Purpose ◽  
Cmos Process ◽  
Vision Chip ◽  
Processing Elements ◽  
Photo Detectors

We have been developing a VLSI device called vision chip in which photo detectors are integrated with paralled processing elements and that realizes high speed robot control using visual feedback. Using a 0.35μm CMOS process, we have developed a 16 × 16 prototype chip and have demonstrated some image acquiring and processing experiments. A vision system which includes the vision chip has also been constructed.

VCS-IV: A real-time vision system using a digital vision chip

2006 ◽  
Vol 89 (6) ◽  
pp. 34-43 ◽  
Author(s):  
Shingo Kagami ◽  
Takashi Komuro ◽  
Yoshihiro Watanabe ◽  
Masatoshi Ishikawa
Keyword(s):  
Real Time ◽  
Vision System ◽  
Vision Chip

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture

2000 ◽  
Vol 12 (5) ◽  
pp. 521-526
Author(s):  
Masanori Hariyama ◽  
◽  
Michitaka Kameyama
Keyword(s):  
Stereo Vision ◽  
Stereo Matching ◽  
Parallel Architecture ◽  
Window Size ◽  
Input Image ◽  
General Purpose ◽  
Image Size ◽  
Matching Algorithm ◽  
Processing Elements ◽  
General Purpose Processor

This article presents a stereo-matching algorithm to establish reliable correspondence between images by selecting a desirable window size for SAD (Sum of Absolute Differences) computation. In SAD computation, parallelism between pixels in a window changes depending on its window size, while parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is proposed to achieve 100% utilization of processing elements. Performance of the VLSI processor is evaluated to be more than 10,000 times higher than that of a general-purpose processor.

scholarly journals A Hybrid Vision Processing Unit with a Pipelined Workflow for Convolutional Neural Network Accelerating and Image Signal Processing

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2989
Author(s):  
Peng Liu ◽  
Yan Song
Keyword(s):  
Signal Processing ◽  
Data Transmission ◽  
High Speed ◽  
High Efficiency ◽  
State Of The Art ◽  
Vision System ◽  
Processing Unit ◽  
Processing Elements ◽  
Vision Processing ◽  
Field Programmable

Vision processing chips have been widely used in image processing and recognition tasks. They are conventionally designed based on the image signal processing (ISP) units directly connected with the sensors. In recent years, convolutional neural networks (CNNs) have become the dominant tools for many state-of-the-art vision processing tasks. However, CNNs cannot be processed by a conventional vision processing unit (VPU) with a high speed. On the other side, the CNN processing units cannot process the RAW images from the sensors directly and an ISP unit is required. This makes a vision system inefficient with a lot of data transmission and redundant hardware resources. Additionally, many CNN processing units suffer from a low flexibility for various CNN operations. To solve this problem, this paper proposed an efficient vision processing unit based on a hybrid processing elements array for both CNN accelerating and ISP. Resources are highly shared in this VPU, and a pipelined workflow is introduced to accelerate the vision tasks. We implement the proposed VPU on the Field-Programmable Gate Array (FPGA) platform and various vision tasks are tested on it. The results show that this VPU achieves a high efficiency for both CNN processing and ISP and shows a significant reduction in energy consumption for vision tasks consisting of CNNs and ISP. For various CNN tasks, it maintains an average multiply accumulator utilization of over 94% and achieves a performance of 163.2 GOPS with a frequency of 200 MHz.

Reconfigurable architectures for parallel execution of image processing tasks

2007 ◽  
Vol 15 (4) ◽  
Author(s):  
M. Gorgoń
Keyword(s):  
Image Processing ◽  
Vision System ◽  
Research Work ◽  
Digital Signal ◽  
General Purpose ◽  
Parallel Execution ◽  
High Definition ◽  
Reconfigurable Computers ◽  
Fine Grain ◽  
Definition Of

AbstractReconfigurable computers are becoming third, after general purpose processors and digital signal processors, programmable computing systems. In the present paper, a new definition of parallelism adequate for fine-grain parallel systems is introduced. Computing power requirements for high definition, real-time vision system are discussed. A survey of reconfigurable solutions for image processing and the latest research work carried on at the AGH Laboratory of Biocybernetics are presented.

General-purpose vision chip architecture for real-time machine vision

1997 ◽  
Vol 12 (6) ◽  
pp. 619-627 ◽  
Author(s):  
Takashi Komuro ◽  
Idaku Ish ◽  
Masatoshi Ishikawa
Keyword(s):  
Machine Vision ◽  
Real Time ◽  
General Purpose ◽  
Time Machine ◽  
Vision Chip
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