Board Level High Speed Photonic Interconnections: Recent System Developments

1990 ◽  
Author(s):  
Gail R. Lalk ◽  
Penny D. Smith ◽  
David W. Emmetts ◽  
Davis H. Hartman
Keyword(s):  
High Speed ◽  
Board Level

Correlating Drop Impact Simulations With Drop Impact Testing Using High-Speed Camera Measurements

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
J. J. M. Zaal ◽  
W. D. van Driel ◽  
F. J. H. G. Kessels ◽  
G. Q. Zhang
Keyword(s):  
High Speed ◽  
Simulation Models ◽  
3D Models ◽  
Drop Impact ◽  
Impact Testing ◽  
Navigation Systems ◽  
High Speed Camera ◽  
Impact Performance ◽  
Impact Simulations ◽  
Board Level

The increased use of mobile appliances such as mobile phones and navigation systems in today’s society has resulted in an increase in reliability issues related to drop performance. Mobile appliances are dropped several times during their lifespan and the product is required to survive common drop accidents. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. This test has been standardized by international councils such as Joint Electron Device Engineering Council and is widely adopted throughout the industry. In this research the solder loading is investigated by combining high-speed camera measurements of several drop impact tests with verified finite element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on interconnect layout, drop conditions, and product specifications prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: machine level (rebounds with and without a catcher) and product level (with different levels of energy and different pulse times). Parametric (dynamic and quasistatic) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g., by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Printed Circuit ◽  
Drop Tests ◽  
Bend Tests ◽  
Board Level

Enhancing High Speed Signal Integrity with Optimized Board Level Power Network Design

2017 ◽  
Vol 23 (6) ◽  
pp. 5019-5023
Author(s):  
Yee Chang Fei ◽  
Asral Bahari Jambek ◽  
Azremi Abdullah Al-Hadi
Keyword(s):  
Network Design ◽  
High Speed ◽  
Signal Integrity ◽  
Power Network ◽  
Board Level

Development of high speed board level bend tester for drop impact applications

2009 ◽  
Author(s):  
Shu Min Lim ◽  
Zhong Chen ◽  
Hun Shen Ng ◽  
Tong Yan Tee ◽  
Choong Peng Khoo ◽  
...  
Keyword(s):  
High Speed ◽  
Drop Impact ◽  
Board Level

Various Levels of Drop Analysis for BGA in Mobile Phones

2007 ◽  
Author(s):  
Takayoshi Katahira ◽  
Masato Fujita ◽  
Tsuyoki Shibata ◽  
Masaki Shiratori ◽  
Qiang Yu
Keyword(s):  
Mobile Phones ◽  
High Speed ◽  
Dielectric Materials ◽  
System Level ◽  
Detailed Model ◽  
Multiple Devices ◽  
Micro Level ◽  
Orthotropic Properties ◽  
Board Level ◽  
Ic Package

To final product quality of mobile phones, key reliability requirements are drop, bend and thermal cycling. Especially in terms of IC-device, drop reliability is the most significant of the three, and also difficult to optimize since it is a dynamic phenomenon in high speed and drop reliability is influenced by 1) system-level factors, 2) board-level and 3) micro-level. In this paper, system-level is defined as phone-level drop, specifically simplified mono-block phone including multiple devices on PWB. System-level enables to evaluate various factors, drop height, drop directions, materials to drop on, phone weight and phone mechanics. Board-level indicates IC-package, PWB and solder joints connecting in between. The board-assembled PWB is fixed onto fixture at 2∼6 points. Drop direction is flat drop only. This paper defines micro level as more detailed model than board level. PWB is modeled as composite structure consisting of dielectric materials with orthotropic properties, copper layers and micro via. IC-package is modeled as well. System level drop shows significant differences in drop directions and also the interactions between drop direction and component location. Micro level simulation results are well-correlative with experimental in failure mode. This paper will discuss overview of 3 levels of drop modeling and will focus on micro level and system level analysis in conjunction with board level.

Board Level High Speed Photonic Interconnections: Recent Technology Developments

1989 ◽  
Author(s):  
David H. Hartman ◽  
Gail R. Lalk ◽  
Thomas C. Banwell ◽  
Ivan Ladany
Keyword(s):  
High Speed ◽  
Board Level

scholarly journals Board-Level Lifetime Prediction for Power Board of Balise Transmission Module in High-Speed Railways

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 135011-135024 ◽  
Author(s):  
Wei Shangguan ◽  
Yu Zang ◽  
Huashen Wang ◽  
Michael G. Pecht
Keyword(s):  
High Speed ◽  
Lifetime Prediction ◽  
Level Lifetime ◽  
Board Level

Design of Universal Signal Processing Machine Based on Multiple DSP

2013 ◽  
Vol 321-324 ◽  
pp. 1241-1244
Author(s):  
Yang Jian ◽  
Yu Hao Liu ◽  
Xi Jing Zhao ◽  
Hao Ming Chen
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Multiple Channel ◽  
Processing Machine ◽  
Large Memory ◽  
High Speed Data ◽  
Board Level

With the development and application of technique on high speed digital signal processing, wide bandwidth processing, high-speed data exchanging and flexible interlink structure have been the developing trend of modern high performance signal processing machine. In this paper, one universal signal processing machine is designed based on six pieces of ADSP-TS201 TigerSHARC processors, which owns good characteristics such as: large memory, excellent processing and data-exchanging performance, reconstitution, good expansibility. This signal processing machine adopts 64Bit, 66MHz CPCI bus standard and supports the function of extending processing performance by interlinking multiple boards. The high-speed data-exchanging is realized with multiple channel optical fiber. Furthermore, it owns board-level BIT function.

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