Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

2008 ◽  
Author(s):  
M. C. Chiu ◽  
Benjamin Szu-Min Lin ◽  
M. F. Tsai ◽  
Y. S. Chang ◽  
M. H. Yeh ◽  
...  
Keyword(s):  
Nand Flash ◽  
Double Patterning

Pattern wiggling investigation of self-aligned double patterning for 2x nm node NAND Flash and beyond

2013 ◽  
Author(s):  
You-Yu Lin ◽  
Chun-Chi Chen ◽  
Chia-Yu Li ◽  
Zih-Song Wang ◽  
Ching-Hua Chen
Keyword(s):  
Nand Flash ◽  
Double Patterning

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning

2009 ◽  
Author(s):  
Shiyu Sun ◽  
Chris Bencher ◽  
Yongmei Chen ◽  
Huixiong Dai ◽  
Man-Ping Cai ◽  
...  
Keyword(s):  
Nand Flash ◽  
Double Patterning

Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

2010 ◽  
Author(s):  
Yi-Shiang Chang ◽  
Jason Sweis ◽  
Jun-Cheng Lai ◽  
Chia-Chi Lin ◽  
Jonathan Yu
Keyword(s):  
Nand Flash ◽  
Pattern Decomposition ◽  
Double Patterning

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems

2016 ◽  
Vol E99.C (2) ◽  
pp. 293-301 ◽  
Author(s):  
Youngjoo LEE ◽  
Jaehwan JUNG ◽  
In-Cheol PARK
Keyword(s):  
Storage Systems ◽  
Nand Flash ◽  
Ldpc Decoding
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