Holograms For Optical Interconnects For Very Large Scale Integrated Circuits Fabricated By Electron-Beam Lithography

1989 ◽  
Vol 28 (8) ◽  
Author(s):  
Michael R. Feldman ◽  
Clark C. Guest
2015 ◽  
Vol 1109 ◽  
pp. 617-625
Author(s):  
Shiro Nagaoka ◽  
Hideo Horibe ◽  
Jin Ping Ao ◽  
Seiichi Tagawa

It is well known that electron beam lithography is one of the potential candidates to fulfill of the demand of the miniaturization of the design rule of semiconductor integrated circuits beyond sub 100nm size with high reproducibility. It is also a fact that the resolution is recognized to depend on the various factors which are oriented to the machine and process conditions, for example, electron beam diameter, the intensity distribution of the beam itself, the resistance properties polymers, the development conditions, etc. Therefore, it is thought that it is impossible to be derivable directly and unambiguously from the resist material itself. In this study, the intrinsic resolution of the resist polymer was discussed based on the hypothesis that the resolution itself may be able to improve to the same size as the size of an electron beam profile, or less. The bi-layer structure ZEP520A/poly methyl glutar imide (PMGI) was proposed and tested. As for the results achieved, the contrast γ was improved constantly with a reduction in the development time and a decrease in the development temperature. The highest γ value, approximately 18, was obtained during development at the-20°C condition. An approximately 70nm with high aspect ratio pattern which is almost the same size of the beam pattern was obtained. This result provides an understanding how the intrinsic resolution of the resist material should be, and can be applied to other lithography methods. This process was applied to the actual electrode pattern making process. An approximately 100nm width of Copper nanowire as the gate electrode for the AlGaN/GaN HFET was successfully demonstrated. In addition, AlGaN/GaN HFET operated at about 73.5GHz, successfully.


1992 ◽  
Vol 260 ◽  
Author(s):  
William H. Haydl ◽  
R. J. Bojko ◽  
L. F. Eastman

ABSTRACTIn the development of air bridges for low capacitance crossovers, resists of 3–6μm thickness a e needed, which calls for special alignment techniques. A technique has been developed for an air bridge tec nology, which is realized entirely by electron beam lithography. Such an all-electron-beam technique for sub-micron devices and ultrahigh frequency circuits, results in a fast turn-around-time in the development of integrated circuits.Gold plated air bridges with 20 to 120 pm span, 5–60 μm width, 2.6 pm height, and 2–4 μm thickness, were realized on GaAs and InP.


Author(s):  
Alec N. Broers

This paper discusses the role of scanning electron beam lithography in semiconductor microcircuit production and in the experimental fabrication of devices in the laboratory. It also describes the electron optical equipment developed for these applications.Electron beam lithography has found an important place in integrated circuit production through its ability to produce structures without masks, rather than because it can produce high resolution. Resolution, however, has been important in research and development where electron beams have been used to produce smaller devices than any other method. Many early micron and sub-micron large scale integration devices were built first with electron beams, and structures as small as a few tens of nanometers have been made for electrical characterization.Optical methods are generally more economical than electron beams for the routine production of microcircuits because exposure rates are higher and system costs are lower. Resolution with optical lithography is adequate for all devices likely to be in production in the next few years (minimum linewidth 0.75μ - 2μ) so electron beams at present only offer an advantage in fabricating masks, or in exposing customized wafers where masks are not replicated a sufficiently large number of times to offset their cost.


The paper discusses and compares the lithography methods being developed for the fabrication of future generations of silicon integrated circuits. The smallest features in today’s circuits are about 0.3 μm in size and this will be reduced to 0.1 μm within the next ten years. The methods discussed include optical (ultraviolet light) projection, which is used predominantly at present, projection printing at wavelengths between the X-ray and ultraviolet regions, X-ray proximity printing, and scanning and projection with electrons and ions. There are severe problems to be overcome with all of the methods before they can satisfy future needs. The difficulties are not just connected with obtaining adequate resolution. The more challenging requirements are those associated with the elimination of distortion in the highly complex trillion pixel images and of achieving an exposure rate of about one per second with a system of acceptable cost, that is less than about $10M. The various approaches for correcting distortion and obtaining adequate throughput are described, as are the factors limiting resolution. Finally, the ultimate capabilities of electron beam methods for fabricating structures and devices with dimensions down to 1 nm are described.


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