An ultra-narrow FinFET poly-Si gate structure fabricated with 193nm photolithography and in-situ PR/BARC and TEOS hard mask etching

2008 ◽  
Author(s):  
Wen-Shiang Liao ◽  
Cheng-Han Wu ◽  
Mao-Chyuan Tang ◽  
Sheng-Yi Huang ◽  
Tommy Shih ◽  
...  
Keyword(s):  
Hard Mask ◽  
Gate Structure ◽  
Mask Etching

A thick CESL stressed ultra-small (Lg=40nm) SiGe-channel MOSFET fabricated with 193nm scanner lithography and TEOS hard mask etching

2007 ◽  
Author(s):  
Wen-Shiang Liao ◽  
Tung-Hung Chen ◽  
Hsin-Hung Lin ◽  
Wen-Tung Chang ◽  
Tommy Shih ◽  
...  
Keyword(s):  
Hard Mask ◽  
Mask Etching

The Role of Oxygen on Anisotropy in Chromium Oxide Hard Mask Etching for Sub-Micron Fabrication

2021 ◽  
Vol 20 ◽  
pp. 33-38
Author(s):  
Huseyin Ekinci ◽  
Navid M.S. Jahed ◽  
Mohammad Soltani ◽  
Bo Cui
Keyword(s):  
Chromium Oxide ◽  
Hard Mask ◽  
Mask Etching

A 20 nm physical gate length NMOSFET with a 1.2 nm gate oxide fabricated by mixed dry and wet hard mask etching

2002 ◽  
Vol 46 (3) ◽  
pp. 349-352 ◽  
Author(s):  
C. Caillat ◽  
S. Deleonibus ◽  
G. Guegan ◽  
M. Heitzmann ◽  
M.E. Nier ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Gate Length ◽  
Hard Mask ◽  
Mask Etching ◽  
20 Nm

“In situ” hard mask materials: a new methodology for creation of vertical silicon nanopillar and nanowire arrays

Nanoscale ◽  
2012 ◽  
Vol 4 (24) ◽  
pp. 7743 ◽  
Author(s):  
Tandra Ghoshal ◽  
Ramsankar Senthamaraikannan ◽  
Matthew T. Shaw ◽  
Justin D. Holmes ◽  
Michael A. Morris
Keyword(s):  
Nanowire Arrays ◽  
Hard Mask

Precise Control and Resizing of Polysilicon Gate Length by Hard-Mask Etching

1998 ◽  
Vol 37 (Part 1, No. 10) ◽  
pp. 5519-5525 ◽  
Author(s):  
Masaaki Sato ◽  
Yoshio Kawai
Keyword(s):  
Gate Length ◽  
Hard Mask ◽  
Precise Control ◽  
Polysilicon Gate ◽  
Mask Etching

Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

2006 ◽  
Vol 504 (1-2) ◽  
pp. 117-120 ◽  
Author(s):  
Vladimir Bliznetsov ◽  
Rakesh Kumar ◽  
Huizhen Lin ◽  
Kah-Wee Ang ◽  
Won Jong Yoo ◽  
...  
Keyword(s):  
Integrated Process ◽  
Hard Mask ◽  
Mask Etching

RESONANT TUNNELING AND COULOMB BLOCKADE IN A NANOCRYSTALLINE Si DOUBLE-BARRIER FLOATING-GATE STRUCTURE

2006 ◽  
Vol 05 (06) ◽  
pp. 853-858
Author(s):  
XINFAN HUANG ◽  
LIANGCAI WU ◽  
MIN DAI ◽  
LINWEI YU ◽  
WEI LI ◽  
...  
Keyword(s):  
Coulomb Blockade ◽  
Electron Tunneling ◽  
Chemical Vapor ◽  
Nanocrystalline Silicon ◽  
Floating Gate ◽  
Double Barrier ◽  
Nanoelectronic Devices ◽  
Gate Structure ◽  
Capacitance Voltage

We report the results of electron tunneling and Coulomb blockade in nanocrystalline silicon ( nc - Si ) double-barrier floating-gate structure ( SiO 2/ nc - Si/SiO 2) fabricated in situ in a plasma-enhanced chemical-vapor-deposition (PECVD) system for the nanoelectronic devices application. The quantum confinement and Coulomb blockade effect have been demonstrated in the capacitance–voltage (C–V) characteristics, in which unique peak structures differ remarkably from the normal smooth C–V curves. The experimental results have been explained by band diagram and equivalent circuits. By contrasted with silicon single electron transistor memory made by using ultra fancy nanotechnology, nc - Si -based memory can be fabricated with a minimum perturbation of conventional silicon technology and may be closest to industrial application.

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