Multi-scale soft-lithographic lift-off and grafting (MS-SLLOG) process for active polymer nanophotonic device fabrication

2005 ◽  
Author(s):  
Yi-Chung Tung ◽  
Steven C. Truxal ◽  
Katsuo Kurabayashi
Keyword(s):  
Device Fabrication ◽  
Multi Scale ◽  
Nanophotonic Device ◽  
Lift Off

scholarly journals Transfer Printing of Semiconductor Nanowires with Lasing Emission for Controllable Nanophotonic Device Fabrication

ACS Nano ◽  
2016 ◽  
Vol 10 (4) ◽  
pp. 3951-3958 ◽  
Author(s):  
Benoit Guilhabert ◽  
Antonio Hurtado ◽  
Dimitars Jevtics ◽  
Qian Gao ◽  
Hark Hoe Tan ◽  
...  
Keyword(s):  
Semiconductor Nanowires ◽  
Device Fabrication ◽  
Transfer Printing ◽  
Nanophotonic Device

scholarly journals Three-Dimensional Device Fabrication in Monocrystalline Diamond Using FIB and a Novel Lift-Off Technique

2005 ◽  
Vol 11 (S02) ◽  
Author(s):  
P Olivero ◽  
S Rubanov ◽  
P Reichard ◽  
S Huntington ◽  
B Gibson ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Device Fabrication ◽  
Lift Off ◽  
Monocrystalline Diamond

scholarly journals 3D Nanophotonic device fabrication using discrete components

Nanophotonics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1373-1390
Author(s):  
Jeffrey E. Melzer ◽  
Euan McLeod
Keyword(s):  
Hybrid Methods ◽  
Three Dimensional ◽  
Directed Assembly ◽  
Building Blocks ◽  
Single Step ◽  
Device Fabrication ◽  
Dimensional Structure ◽  
Nanophotonic Devices ◽  
Nanophotonic Device ◽  
Nanophotonic Structures

AbstractThree-dimensional structure fabrication using discrete building blocks provides a versatile pathway for the creation of complex nanophotonic devices. The processing of individual components can generally support high-resolution, multiple-material, and variegated structures that are not achievable in a single step using top-down or hybrid methods. In addition, these methods are additive in nature, using minimal reagent quantities and producing little to no material waste. In this article, we review the most promising technologies that build structures using the placement of discrete components, focusing on laser-induced transfer, light-directed assembly, and inkjet printing. We discuss the underlying principles and most recent advances for each technique, as well as existing and future applications. These methods serve as adaptable platforms for the next generation of functional three-dimensional nanophotonic structures.

Multi-Scale Transient Thermal Analysis of Microelectronics

2012 ◽  
Author(s):  
Banafsheh Barabadi ◽  
Satish Kumar ◽  
Valeriy Sukharev ◽  
Yogendra K. Joshi
Keyword(s):  
Flip Chip ◽  
Computational Cost ◽  
Close Correlation ◽  
Device Fabrication ◽  
Fe Model ◽  
Computationally Efficient ◽  
Suggested Approach ◽  
Multi Scale ◽  
Microelectronic Devices ◽  
Transient Thermal

Thermal transport in microelectronic devices spans length scales from tens of nanometers to hundreds of millimeters. One of the major challenges in maintaining quality and reliability in today’s microelectronic devices comes from the ever increasing level of integration in the device fabrication as well as the high level of current densities that are carried through the microchip during operation. Consequently, significant opportunities for energy efficiency exist at various levels of the length scale hierarchy by optimization of thermal management resources. In this study, we developed a computationally efficient and accurate multi-scale reduced order transient thermal methodology consisting of hybrid implementation of two different multi-scale approaches: 1. “Progressive Zoom-in” method and 2. “Proper Orthogonal Decomposition (POD)” technique. The suggested approach provides the ability to predict different thermal scenarios based on one representative thermal scenario, while maintaining the desired spatial and temporal accuracy. In this paper, a Flip Chip Ball Grid Array (FCBGA) package was considered for hybrid modeling. To demonstrate the capability of POD method in predicting different thermal scenarios, the chip is divided into ten function blocks. Each of these blocks had a different randomly generated dynamic power source. To validate this methodology, the results were compared with a finite element (FE) model developed in COMSOL®. The behavior of the POD model was in good agreements with the corresponding FE model. This close correlation provides the capability of predicting other thermal scenarios based on a smaller sample set which can significantly decrease the computational cost.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Effects of substrate quality and annealing on defect structures at GaAs/Si interfaces

1987 ◽  
Vol 45 ◽  
pp. 340-341
Author(s):  
H. L. Tsai ◽  
J. W. Lee
Keyword(s):  
Growth Process ◽  
Molecular Beam ◽  
Substrate Surface ◽  
Lattice Misfit ◽  
Device Fabrication ◽  
Silicon Substrates ◽  
Defect Structures ◽  
Gaas Film ◽  
Substrate Quality ◽  
Gaas On Si

Growth of GaAs on Si using epitaxial techniques has been receiving considerable attention for its potential application in device fabrication. However, because of the 4% lattice misfit between GaAs and Si, defect generation at the GaAs/Si interface and its propagation to the top portion of the GaAs film occur during the growth process. The performance of a device fabricated in the GaAs-on-Si film can be degraded because of the presence of these defects. This paper describes a HREM study of the effects of both the substrate surface quality and postannealing on the defect propagation and elimination.The silicon substrates used for this work were 3-4 degrees off [100] orientation. GaAs was grown on the silicon substrate by molecular beam epitaxy (MBE).

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