<title>A deterministic BIST scheme for test time reduction in VLSI circuits</title>

Versuchszeit reduzieren - Möglichkeiten und Grenzen / Test Time Reduction - Chances and Limits

Materials Testing ◽

10.1515/mt-1998-400607 ◽

1998 ◽

Vol 40 (6) ◽

pp. 240-244

Author(s):

H Zenner

Keyword(s):

Test Time ◽

Test Time Reduction ◽

Time Reduction

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FPGA test time reduction through a novel interconnect testing scheme

Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02 ◽

10.1145/503048.503069 ◽

2002 ◽

Cited By ~ 8

Author(s):

Stuart McCracken ◽

Zeljko Zilic

Keyword(s):

Test Time ◽

Interconnect Testing ◽

Testing Scheme ◽

Test Time Reduction ◽

Time Reduction

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An efficient scan tree design for test time reduction

Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. ◽

10.1109/etsym.2004.1347657 ◽

2004 ◽

Cited By ~ 22

Author(s):

Y. Bonhomme ◽

T. Yoneda ◽

H. Fujiwara ◽

P. Girard

Keyword(s):

Test Time ◽

Design For Test ◽

Test Time Reduction ◽

Time Reduction

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2.2.1 Test time reduction by optimal test sequencing1

INCOSE International Symposium ◽

10.1002/j.2334-5837.2006.tb02741.x ◽

2006 ◽

Vol 16 (1) ◽

pp. 259-269 ◽

Cited By ~ 1

Author(s):

R. Boumen ◽

I.S.M. de Jong ◽

J.M. van de Mortel-Fronczak ◽

J.E. Rooda

Keyword(s):

Test Time ◽

Optimal Test ◽

Test Time Reduction ◽

Time Reduction

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Test time reduction methods for yield test structures

International Conference on Microelectronic Test Structures, 2003. ◽

10.1109/icmts.2003.1197384 ◽

2003 ◽

Cited By ~ 4

Author(s):

C. Hess ◽

H. Read ◽

J. Ren ◽

L.H. Weiland ◽

Jianjun Cheng ◽

...

Keyword(s):

Test Time ◽

Test Time Reduction ◽

Yield Test ◽

Reduction Methods ◽

Time Reduction

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Methods for memory test time reduction

IEEE International Workshop on Memory Technology, Design and Testing, ◽

10.1109/mtdt.1996.782494 ◽

2005 ◽

Cited By ~ 1

Author(s):

Wen-Jer Wu ◽

Chuan Yi Tang ◽

M.Y. Lin

Keyword(s):

Memory Test ◽

Test Time ◽

Test Time Reduction ◽

Time Reduction

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Automated test development and test time reduction for RF subsystems

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

10.1109/iscas.2002.1009907 ◽

2003 ◽

Cited By ~ 10

Author(s):

S. Ozev ◽

A. Orailoglu ◽

H. Haggag

Keyword(s):

Test Development ◽

Test Time ◽

Test Time Reduction ◽

Automated Test ◽

Time Reduction

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Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197628 ◽

2003 ◽

Cited By ~ 7

Author(s):

M. Sharma ◽

J.H. Patel ◽

J. Rearick

Keyword(s):

Data Compression ◽

Test Data ◽

Test Time ◽

Test Data Compression ◽

Test Time Reduction ◽

Longest Path ◽

Time Reduction

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Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction

Integration ◽

10.1016/j.vlsi.2017.06.006 ◽

2017 ◽

Vol 59 ◽

pp. 198-205

Author(s):

S.H. Goh ◽

Y.H. Chan ◽

Zhao Lin ◽

Jeffrey Lam

Keyword(s):

Test Time ◽

Self Testing ◽

Test Time Reduction ◽

Time Reduction

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Functional Fmax test-time reduction using novel DFTs for circuit initialization

2013 IEEE 31st International Conference on Computer Design (ICCD) ◽

10.1109/iccd.2013.6657017 ◽

2013 ◽

Cited By ~ 1

Author(s):

Ujjwal Guin ◽

Tapan Chakraborty ◽

Mohammad Tehranipoor

Keyword(s):

Test Time ◽

Test Time Reduction ◽

Time Reduction

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