Wafer-level packaging of pressure sensor using SU8 photoresist

2005 ◽  
Author(s):  
Ciprian I. Iliescu ◽  
Francis E. H. Tay ◽  
Jianmin Miao ◽  
Marioara Avram
Keyword(s):  
Pressure Sensor ◽  
Wafer Level ◽  
Wafer Level Packaging

A Packaging Solution for Pressure Sensor MEMS

2003 ◽  
Author(s):  
J. Wei ◽  
G. J. Qi ◽  
Z. F. Wang ◽  
Y. F. Jin ◽  
P. C. Lim ◽  
...  
Keyword(s):  
Pressure Sensor ◽  
Bonding Temperature ◽  
Aluminum Film ◽  
Wafer Level ◽  
Whole Process ◽  
Wafer Level Packaging ◽  
Solder Bumps ◽  
Via Holes ◽  
Free Interfaces ◽  
Koh Etching

In this paper, a wafer-level packaging solution for pressure sensor microelectromechanical system (MEMS) is reported. Sensor and glass cap wafers are anodically bonded at a bonding temperature less than 400°C. Bubble free interfaces are obtained and the bond strength is higher than 20 MPa. Sensor and bottom silicon cap wafers are bonded at a temperature of 400–450°C with the assistance of a gold intermediate layer. The bond strenght is higher than 5 MPa. The via holes, used for feedthroughs leading out the circuit, on bottom silicon cap wafer are anisotropically formed in KOH etching solution. Aluminum layer is sputtered on the bottom silicon wafer for electrical connection, re-routing circuit and the seed layer of under bump metallization (UBM). During sputtering process, the sidewalls of via holes are also sputtered with aluminum film. At the same time, the metal pads on sensor wafer are also built up to connect with metallized via holes. It is found that the cavities are vacuum sealed. Sputtered Cr/Ni/Au layers are used for UBM layers. Finally, solder bumps can printed or plated on the UBM. The whole process leads to promising performance of the devices.

Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects

2011 ◽  
Vol 2011 (1) ◽  
pp. 000033-000043 ◽  
Author(s):  
Tao WANG ◽  
Jian CAI ◽  
Qian WANG ◽  
Hao ZHANG ◽  
Zheyao WANG
Keyword(s):  
Pressure Sensor ◽  
Flip Chip ◽  
Electrical Signal ◽  
Sensor System ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Bonding Structure ◽  
Wafer Level Packaging ◽  
Piezoresistive Pressure Sensor ◽  
Processing Circuit

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.

Pirani pressure sensor for smart wafer-level packaging

2009 ◽  
Vol 156 (1) ◽  
pp. 201-207 ◽  
Author(s):  
F. Mailly ◽  
N. Dumas ◽  
N. Pous ◽  
L. Latorre ◽  
O. Garel ◽  
...  
Keyword(s):  
Pressure Sensor ◽  
Wafer Level ◽  
Wafer Level Packaging

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

Sign in / Sign up

Export Citation Format

Share Document