System-level verification methodology for advanced switch fabrics

2003 ◽  
Author(s):  
Javier Sosa ◽  
Juan A. Montiel-Nelson ◽  
Hector Navarro ◽  
Mahendra V. Shahdadpuri ◽  
Roberto Sarmiento
Keyword(s):  
System Level ◽  
Switch Fabrics ◽  
Verification Methodology

An assertion-based verification methodology for system-level design

2007 ◽  
Vol 33 (4) ◽  
pp. 269-284 ◽  
Author(s):  
Amir Masoud Gharehbaghi ◽  
Benyamin Hamdin Yaran ◽  
Shaahin Hessabi ◽  
Maziar Goudarzi
Keyword(s):  
System Level ◽  
System Level Design ◽  
Level Design ◽  
Verification Methodology

Where do we stand? Comparing system-level service lines in the private sector and in VHA

1998 ◽  
Author(s):  
Martin P. Charns ◽  
Victoria A. Parker ◽  
William H. Wubbenhorst
Keyword(s):  
Private Sector ◽  
System Level

Resilient futures: An individual and system-level approach to improve the well-being and resilience of disadvantaged young Australians.

2018 ◽  
Vol 4 (3) ◽  
pp. 228-244 ◽  
Author(s):  
Ivan J. Raymond ◽  
Matthew Iasiello ◽  
Aaron Jarden ◽  
David Michael Kelly
Keyword(s):  
Well Being ◽  
System Level

Gradient based system-level diagnosis

2007 ◽  
Vol 51 (1-2) ◽  
pp. 43
Author(s):  
Balázs Polgár ◽  
Endre Selényi
Keyword(s):  
System Level ◽  
Gradient Based

Interconnect Limits on Gigascale Integration (GSI)

1997 ◽  
Vol 473 ◽  
Author(s):  
J. A. Davis ◽  
J. D. Meindl
Keyword(s):  
Response Time ◽  
Length Distribution ◽  
Path Model ◽  
System Level ◽  
Wire Length ◽  
Clock Frequency ◽  
Gigascale Integration ◽  
Logic Network ◽  
Binary Switching ◽  
Quantitative Definition

ABSTRACTOpportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

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