Clearing the clutter: Unified modeling and verification methodology for system level hardware design

This chapter reviews Information Systems (IS) modeling techniques, including relational algebra, structured design, architectural design, and Unified Modeling Language. A new technique “info-mathics” (i.e.,mathematical description of the hierarchical systems architecture) is defined to secure the system reliability and quality. The classification of IS categories and its attributes such as components, structure, relationships, system level, system product, system deepness, system width, system list, system end, and other are presented. Examples of the mathematical notations are provided and their meaning for the practical implications of info-mathics in system analysis and design are indicated.

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Efficient system-level functional verification methodology for multimedia applications

IEEE Design & Test of Computers ◽

10.1109/mdt.2003.1188263 ◽

2003 ◽

Vol 20 (2) ◽

pp. 56-64 ◽

Cited By ~ 3

Author(s):

M. Cupak ◽

F. Catthoor ◽

H.J. De Man

Keyword(s):

Multimedia Applications ◽

System Level ◽

Functional Verification ◽

Efficient System ◽

Verification Methodology

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MODEL DAN SIMULASI PERBANDINGAN PROTOTYPE RANGKAIAN DIGITAL HALF ADDER ALU STANDAR DENGAN INOVASI RANGKAIAN DIGITAL HALF ADDER ALU

JURNAL TEKNOLOGI INFORMASI ◽

10.36294/jurti.v2i1.414 ◽

2018 ◽

Vol 2 (1) ◽

pp. 1

Author(s):

Helmi Fauzi Siregar ◽

Muhammad Dedi Irawan

Keyword(s):

Comparative Method ◽

Unified Modeling Language ◽

Hardware Design ◽

System Innovation ◽

Modeling Language ◽

Unified Modeling ◽

Half Adder ◽

Descriptive Method ◽

Standard Prototype

Abstract - This research was conducted to model and simulate the Half Adder system. This system is designed by analyzing the descriptive method, and the comparative method. After analysis, modeling is done with UML (Unified Modeling Language) and hardware design based on microcontroller can be programmed using CodeVisionAVR-C software. The results of this study are a standard prototype Half ALU ALTER Adder system that uses XOR, AND, OR gates with ALU Half Adder system innovation using NAND and NOR gates.Keywords - Half Adder, Prototype, XOR, AND, OR, NAND, NOR

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Design and use of a system-level specification and verification methodology

Proceedings of EURO-DAC. European Design Automation Conference ◽

10.1109/eurdac.1995.527449 ◽

2002 ◽

Cited By ~ 10

Author(s):

M.M.K. Hashmi ◽

A.C. Bruce

Keyword(s):

System Level ◽

Specification And Verification ◽

Verification Methodology

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An efficient hardware design approach from system-level specification

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg ◽

10.1109/mwscas.1997.662298 ◽

2005 ◽

Author(s):

Ming-Hwa Sheu ◽

Ming-Der Shieh ◽

Sheng-Wei Liu ◽

Chie Dou

Keyword(s):

Hardware Design ◽

Design Approach ◽

System Level

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An assertion-based verification methodology for system-level design

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2007.02.002 ◽

2007 ◽

Vol 33 (4) ◽

pp. 269-284 ◽

Cited By ~ 5

Author(s):

Amir Masoud Gharehbaghi ◽

Benyamin Hamdin Yaran ◽

Shaahin Hessabi ◽

Maziar Goudarzi

Keyword(s):

System Level ◽

System Level Design ◽

Level Design ◽

Verification Methodology

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Integrating SDL and VHDL for System-Level Hardware Design

Computer Hardware Description Languages and their Applications ◽

10.1016/b978-0-444-81641-2.50021-6 ◽

1993 ◽

pp. 187-204 ◽

Cited By ~ 27

Author(s):

Wolfgang Glunz ◽

Thomas Kruse ◽

Torsten Rössel ◽

Dieter Monjau

Keyword(s):

Hardware Design ◽

System Level

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System-Level Hardware Design with µ-Charts

Hardware Description Languages and their Applications ◽

10.1007/978-0-387-35064-6_7 ◽

1997 ◽

pp. 77-79 ◽

Cited By ~ 3

Author(s):

Jan Philipps ◽

Peter Scholz

Keyword(s):

Hardware Design ◽

System Level

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GENERATION OF TEST CASES USING ACTIVITY DIAGRAM

International Journal of Computer Science and Informatics ◽

10.47893/ijcsi.2014.1172 ◽

2014 ◽

pp. 35-44

Author(s):

RANJITA KUMARI SWAIN ◽

VIKAS PANTHI ◽

PRAFULLA KUMAR BEHERA

Keyword(s):

Soft Drink ◽

Unified Modeling Language ◽

Control Flow ◽

System Level ◽

Test Cases ◽

Flow Graph ◽

Activity Diagram ◽

Unified Modeling ◽

Path Coverage ◽

Uml Activity Diagram

As Unified Modeling Language (UML) activity diagrams capture the key system behavior, the UML activity diagram is well suited for the system level testing of systems. In this paper, first an activity flow graph is derived from activity diagram. Then, all the required information is extracted from the activity flow graph (AFG). The activity flow graph (AFG) for the activity diagram is created by traversing the activity diagram from beginning to end, showing choices, conditions, concurrent executions, loop statements. From the graph different control flow sequence are identified by traversing the AFG by depth first traversal technique. Next, an algorithm is proposed to generate all activity paths. Finally, test cases are generated using activity path coverage criteria. Here, a case study on Soft drink Vending Machine (SVM) has been presented to illustrate our approach.

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