New scalable systolic array processor architecture for simultaneous discrete convolution of k different (n × n) filter coefficient planes with a single image plane

2003 ◽  
Author(s):  
Albert T. Wong ◽  
J. R. Heath ◽  
Michael E. Lhamon
Keyword(s):  
Systolic Array ◽  
Image Plane ◽  
Array Processor ◽  
Processor Architecture ◽  
Filter Coefficient ◽  
Single Image ◽  
Discrete Convolution

Low-power systolic array processor architecture for FSBM video motion estimation

2006 ◽  
Vol 42 (20) ◽  
pp. 1146 ◽  
Author(s):  
M. Jiang ◽  
D. Crookes ◽  
S. Davidson ◽  
R. Turner
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Systolic Array ◽  
Array Processor ◽  
Processor Architecture

Multipath suppression performance of an adaptive array antenna with a systolic array processor

1993 ◽  
Vol 76 (11) ◽  
pp. 95-104
Author(s):  
Manabu Ohmiya ◽  
Tatsuya Kawabata ◽  
Yasutaka Ogawa ◽  
Kiyohiko Itoh
Keyword(s):  
Systolic Array ◽  
Array Antenna ◽  
Adaptive Array ◽  
Array Processor
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