Low-power systolic array processor architecture for FSBM video motion estimation

2006 ◽  
Vol 42 (20) ◽  
pp. 1146 ◽  
Author(s):  
M. Jiang ◽  
D. Crookes ◽  
S. Davidson ◽  
R. Turner
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Systolic Array ◽  
Array Processor ◽  
Processor Architecture

Low-Power Motion Estimation Processor with 3D Stacked Memory

2015 ◽  
Vol E98.A (7) ◽  
pp. 1431-1441 ◽  
Author(s):  
Shuping ZHANG ◽  
Jinjia ZHOU ◽  
Dajiang ZHOU ◽  
Shinji KIMURA ◽  
Satoshi GOTO
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Stacked Memory

Low power sensor node processor architecture

2010 ◽  
Author(s):  
Goran Panic ◽  
Thomas Basmer ◽  
Klaus Tittelbach-Helmrich ◽  
Lukasz Lopacinski
Keyword(s):  
Low Power ◽  
Sensor Node ◽  
Processor Architecture ◽  
Power Sensor

scholarly journals Low Power Digital Multimedia Telecommunication Designs

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 301-315 ◽  
Author(s):  
Koon-Shik Cho ◽  
Jun-Dong Cho
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Communication Systems ◽  
Matched Filter ◽  
Optimization Technique ◽  
Low Power Design ◽  
Multimedia Systems ◽  
Wireless Multimedia ◽  
Design Constraint ◽  
Power Capability

The increasing prominence of wireless multimedia systems and the need to limit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design. Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless multimedia systems leads to much higher power consumption than traditional portable applications. This paper presents possible optimization technique to reduce the energy consumption for wireless multimedia communication systems. Four topics are presented in the wireless communication systems subsection which deal with architectures such as PN acquisition, parallel correlator, matched filter and channel coding. Two topics include the IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as using hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the sample storage in parallel correlator, using complex matched filter that analog operational circuits controlled by digital signals, adopting bit serial arithmetic for the ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA iteration in turbo decoder, using codesign in RS codec, disabling the processing elements as soon as the distortion values become great than the minimum distortion value in motion estimation, and exploiting the relative occurrence of zero-valued DCT coefficient in IDCT.

A Novel Low-Power Motion Estimation Design for H.264

2007 ◽  
Author(s):  
Maria G. Koziri ◽  
Adonios N. Dadaliaris ◽  
Georgios I. Stamoulis ◽  
Ioannis X. Katsavounidis
Keyword(s):  
Motion Estimation ◽  
Low Power
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