Accuracy of diffused aerial image model for full-chip-level optical proximity correction

2000 ◽  
Author(s):  
Jee-Suk Hong ◽  
Hee-Bom Kim ◽  
Hyoung-Soon Yune ◽  
Chang-Nam Ahn ◽  
Young-Mo Koo ◽  
...  
2010 ◽  
Author(s):  
Anatoly Y. Bourov ◽  
Liang Li ◽  
Zhiyong Yang ◽  
Fan Wang ◽  
Lifeng Duan
Keyword(s):  

1994 ◽  
Author(s):  
Eytan Barouch ◽  
Uwe Hollerbach ◽  
Steven A. Orszag
Keyword(s):  

1996 ◽  
Author(s):  
Tetsuro Hanawa ◽  
Kazuya Kamon ◽  
Akihiro Nakae ◽  
Shuji Nakao ◽  
Koichi Moriizumi

Author(s):  
P.J. Phillips ◽  
J. Huang ◽  
S. M. Dunn

In this paper we present an efficient algorithm for automatically finding the correspondence between pairs of stereo micrographs, the key step in forming a stereo image. The computation burden in this problem is solving for the optimal mapping and transformation between the two micrographs. In this paper, we present a sieve algorithm for efficiently estimating the transformation and correspondence.In a sieve algorithm, a sequence of stages gradually reduce the number of transformations and correspondences that need to be examined, i.e., the analogy of sieving through the set of mappings with gradually finer meshes until the answer is found. The set of sieves is derived from an image model, here a planar graph that encodes the spatial organization of the features. In the sieve algorithm, the graph represents the spatial arrangement of objects in the image. The algorithm for finding the correspondence restricts its attention to the graph, with the correspondence being found by a combination of graph matchings, point set matching and geometric invariants.


2018 ◽  
Vol 2018 (16) ◽  
pp. 296-1-296-5
Author(s):  
Megan M. Fuller ◽  
Jae S. Lim
Keyword(s):  

Author(s):  
Hui Pan ◽  
Thomas Gibson

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.


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