<title>500-Mb/s 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry</title>

A 500 Mb/s 10/32 channel, 0.5 μm CMOS VCSEL driver with built-in self-test and clock generation circuitry

Conference Proceedings. LEOS'98. 11th Annual Meeting. IEEE Lasers and Electro-Optics Society 1998 Annual Meeting (Cat. No.98CH36243) ◽

10.1109/leos.1998.737784 ◽

2002 ◽

Cited By ~ 1

Author(s):

F.E. Kiamilev

Keyword(s):

Clock Generation ◽

Self Test ◽

Built In Self Test

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A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry

IEEE Journal of Selected Topics in Quantum Electronics ◽

10.1109/2944.778308 ◽

1999 ◽

Vol 5 (2) ◽

pp. 287-295 ◽

Cited By ~ 12

Author(s):

F.E. Kiamilev ◽

A.V. Krishnamoorthy

Keyword(s):

High Speed ◽

Clock Generation ◽

Self Test ◽

Built In Self Test

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Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2014.0308083 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11487-11495

Author(s):

S. Nagaraju ◽

Ch.N.L. Sujatha ◽

J.S.S. Ramaraju

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Benchmark Circuit ◽

Self Test ◽

Built In Self Test

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Memory Implementation in a System on Chip with Built-in Self-Test and Recovery Tools

Proceedings of Universities ELECTRONICS ◽

10.24151/1561-5405-2019-24-3-239-247 ◽

2019 ◽

Vol 24 (3) ◽

pp. 239-247

Author(s):

Vladimir G. Ryabtsev ◽

◽

Sergey V. Volobuev ◽

Keyword(s):

System On Chip ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Recovery Tools

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RF Phase Error Built-In-Self-Test for A GSM SOC

i-manager’s Journal on Electrical Engineering ◽

10.26634/jee.1.4.378 ◽

2008 ◽

Vol 1 (4) ◽

pp. 39-44

Author(s):

Dallas Webster ◽

Loi Phan ◽

Oren Eliezer ◽

Rick Hudgens ◽

Donald Lie

Keyword(s):

Phase Error ◽

Self Test ◽

Built In Self Test

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Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3427911 ◽

2021 ◽

Vol 26 (3) ◽

pp. 1-18

Author(s):

Mehmet Ince ◽

Ender Yilmaz ◽

Wei Fu ◽

Joonsung Park ◽

Krishnaswamy Nagaraj ◽

...

Keyword(s):

Phase Locked Loops ◽

Test And Evaluation ◽

Self Test ◽

Built In Self Test

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IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270909 ◽

2004 ◽

Cited By ~ 5

Author(s):

J.J. Nejedlo

Keyword(s):

Next Generation ◽

Pci Express ◽

Self Test ◽

Built In Self Test ◽

Test Architecture ◽

Generation Test

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Built-in-self-test 3-D ring oscillator for stacked 3DIC

2014 IEEE International Symposium on Radio-Frequency Integration Technology ◽

10.1109/rfit.2014.6933251 ◽

2014 ◽

Author(s):

Cheng Jin ◽

Ni Wang ◽

Xiaowen Xu ◽

Houjun Sun

Keyword(s):

Ring Oscillator ◽

Self Test ◽

Built In Self Test

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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763109 ◽

2011 ◽

Cited By ~ 29

Author(s):

A Strano ◽

C Gómez ◽

D Ludovici ◽

M Favalli ◽

M E Gómez ◽

...

Keyword(s):

Network On Chip ◽

Structural Redundancy ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Test Architecture

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A 2-15 GHz built-in-self-test system for wide-band phased arrays using self-correcting 8-state I/Q mixers

2016 IEEE MTT-S International Microwave Symposium (IMS) ◽

10.1109/mwsym.2016.7540430 ◽

2016 ◽

Cited By ~ 2

Author(s):

Tumay Kanar ◽

Gabriel M. Rebeiz

Keyword(s):

Phased Arrays ◽

Wide Band ◽

Test System ◽

Self Test ◽

Built In Self Test

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