Back-side emission from filtered gold targets

1997 ◽  
Author(s):  
Stephen J. Moon ◽  
David C. Eder
Keyword(s):  
Author(s):  
Wong Yaw Yuan ◽  
T.L. Edmund Poh ◽  
David Lam

Abstract The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.


2020 ◽  
Vol 2020 (1) ◽  
pp. 000181-000184
Author(s):  
F.R. Libsch ◽  
S.W. Bedell ◽  
B.C. Webb ◽  
A. Paidimarri

Abstract This paper discusses some design and implementation issues related to GaN micro-LED (μLED) incorporated into the heterogeneous packaging of IBM’s smart and secure sensor platform. For cost effective μLEDs, the sapphire substrate needs to be singulated reliably and with minimum kerf perimeter, be ultra-clean and smooth to allow back side emission without scattering, and high yielding front side flip chip bonding with 20μm C4s on 40μm pitch. The GaN μLEDs are design for low voltage/low power operation with an emission area of 20μm × 20μm with critical current density of ~10nA/μm2. Power and downlink data is delivered to the system via optical energy harvesting by on-silicon carrier photovoltaics and communication photodiode, respectively. Optical amplitude modulated uplink communication by heterogeneous packaging of the GaN μLED with a 14nm CMOS smart chip will be detailed and demonstrated in presentation.


1996 ◽  
Author(s):  
Nevil M. Wu ◽  
Kenneth Tang ◽  
James H. Lin

Author(s):  
N.M. Wu ◽  
K. Weaver ◽  
J.H. Lin

Abstract With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.


Author(s):  
M. H. Rhee ◽  
W. A. Coghlan

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.


2019 ◽  
Author(s):  
Yan Wang ◽  
Sagar Udyavara ◽  
Matthew Neurock ◽  
C. Daniel Frisbie

<div> <div> <div> <p> </p><div> <div> <div> <p>Electrocatalytic activity for hydrogen evolution at monolayer MoS2 electrodes can be enhanced by the application of an electric field normal to the electrode plane. The electric field is produced by a gate electrode lying underneath the MoS2 and separated from it by a dielectric. Application of a voltage to the back-side gate electrode while sweeping the MoS2 electrochemical potential in a conventional manner in 0.5 M H2SO4 results in up to a 140-mV reduction in overpotential for hydrogen evolution at current densities of 50 mA/cm2. Tafel analysis indicates that the exchange current density is correspondingly improved by a factor of 4 to 0.1 mA/cm2 as gate voltage is increased. Density functional theory calculations support a mechanism in which the higher hydrogen evolution activity is caused by gate-induced electronic charge on Mo metal centers adjacent the S vacancies (the active sites), leading to enhanced Mo-H bond strengths. Overall, our findings indicate that the back-gated working electrode architecture is a convenient and versatile platform for investigating the connection between tunable electronic charge at active sites and overpotential for electrocatalytic processes on ultrathin electrode materials.</p></div></div></div><br><p></p></div></div></div>


Author(s):  
J.S. McMurray ◽  
C.M. Molella

Abstract Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.


Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.


Author(s):  
Jamey Moss ◽  
Sam Subramanian ◽  
Vince Soorholtz ◽  
Michael Thomas ◽  
Mark Gerber ◽  
...  

Abstract Several hundred units were subjected to autoclave stress as part of the qualification of a new fast static RAM. Many units failed after autoclave stress, and these parts recovered after conventional depotting using nitric acid and a hot plate. Based on the recovery of the units, the failures were determined to be fuse-related because the nitric acid cleared the fuse cavities during depotting. Chemical analysis after thermally extracting the die from the package revealed an antimony-rich material in failing fuse cavities. Source of the antimony was linked to antimony trioxide added to the plastic package as a fire retardant. However, it was unclear whether the antimony-rich material caused the failure or if it was an artifact of thermal depotting. A new approach that did not thermally or chemically alter the fuse cavities was employed to identify the failing fuses. This approach used a combination of back-side grinding, dimpling, and back-side microprobing. The antimony-rich material found in the fuse cavity was confirmed using SEM and TEM-based EDS analysis, and it is believed to be a major contributing factor to fuse failures. However, it is unclear whether the short was caused by the antimony-rich material or by a reaction between that material and residual aluminum (oxide) left in the fuse cavity after the laser blows.


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