Wafer-level curved sensor manufacturing process for enhanced optical system designs

2021 ◽  
Author(s):  
Wilfried Jahn ◽  
Michael Bailly ◽  
Gregoire Hein
Keyword(s):  
Optical System ◽  
Manufacturing Process ◽  
Wafer Level ◽  
System Designs

Design Optimization of Off-Chip Inductors

2003 ◽  
Author(s):  
Lin Jin ◽  
Albert Chee W. Lu ◽  
Lai L. Wai ◽  
Wei Fan ◽  
Aik Chong Tan ◽  
...  
Keyword(s):  
Design Optimization ◽  
Manufacturing Process ◽  
Design Methodology ◽  
Solution Space ◽  
Operating Frequency ◽  
Wafer Level ◽  
Space Design ◽  
Electromagnetic Simulations

A solution space design methodology is presented for optimization of off-chip inductors. The analysis has been performed for an advanced wafer level redistribution manufacturing process. Electromagnetic simulations were performed to extract the characteristics of different inductor designs. It was observed that the design optimization should be tuned to the operating frequency.

Leveraging wafer-level manufacturing process limitations to increase large-scale fused silica microlens array uniformity

2019 ◽  
Author(s):  
Raoul Kirner ◽  
Jeremy Béguelin ◽  
Wilfried Noell ◽  
Martin Eisner ◽  
Toralf Scharf ◽  
...  
Keyword(s):  
Manufacturing Process ◽  
Large Scale ◽  
Microlens Array ◽  
Fused Silica ◽  
Wafer Level

Study of an infrared hybrid chalcogenide silicon lenses compatible with wafer-level manufacturing process for automotive applications

2021 ◽  
Author(s):  
Guillaume Druart ◽  
Florence de la Barrière ◽  
Jean-Baptiste C. G. Volatier ◽  
Elodie Tartas ◽  
Raphaël Proux ◽  
...  
Keyword(s):  
Manufacturing Process ◽  
Automotive Applications ◽  
Wafer Level ◽  
Silicon Lenses

scholarly journals Si-based Ka-band SIW band-pass filter using wafer level manufacturing process

2021 ◽  
Vol 18 (1) ◽  
pp. 20200414-20200414
Author(s):  
Hanxiang Zhu ◽  
Jun Li ◽  
Liqiang Cao ◽  
Jia Cao ◽  
Pengwei Chen
Keyword(s):  
Manufacturing Process ◽  
Band Pass Filter ◽  
Wafer Level ◽  
Pass Filter ◽  
Ka Band ◽  
Band Pass

Optical system designs based on bi-directional sensor devices

2012 ◽  
Author(s):  
Constanze Grossmann ◽  
Ute Gawronski ◽  
Franziska Perske ◽  
Gunther Notni ◽  
Andreas Tünnermann
Keyword(s):  
Optical System ◽  
Sensor Devices ◽  
System Designs ◽  
Directional Sensor

Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging

2017 ◽  
Vol 2017 (1) ◽  
pp. 000721-000726 ◽  
Author(s):  
Chet Palesko ◽  
Amy Lujan
Keyword(s):  
Manufacturing Process ◽  
Cost Comparison ◽  
Wafer Level ◽  
Cost Drivers ◽  
Wafer Level Packaging ◽  
Market Requirements ◽  
And Performance ◽  
The Cost

Abstract Fan-out wafer-level packaging (FOWLP) and embedded die packaging offer similar advantages over traditional packaging technologies. For example, both packages can be quite thin since the die is placed early in the manufacturing process and the package is fabricated around the die. This is in contrast to traditional packaging technologies, in which the package is fabricated first, and then the die is placed on top of the package. This results in a thicker package compared to fabricating the package around the die. Due to the ongoing miniaturization market requirements, thinner packages are becoming increasingly important. Both FOWLP and embedded die packaging also provide the capability of placing multiple die and passives in a single package. This capability can have both size and performance benefits since the interconnect distance between the embedded components is shorter. In this paper, the cost and cost drivers of FOWLP and embedded die packaging technologies will be compared. Activity based modeling will be used to characterize the cost of each activity in the two manufacturing flows.

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