Leveraging wafer-level manufacturing process limitations to increase large-scale fused silica microlens array uniformity

2019 ◽  
Author(s):  
Raoul Kirner ◽  
Jeremy Béguelin ◽  
Wilfried Noell ◽  
Martin Eisner ◽  
Toralf Scharf ◽  
...  
Keyword(s):  
Manufacturing Process ◽  
Large Scale ◽  
Microlens Array ◽  
Fused Silica ◽  
Wafer Level

High power supercontinuum generation by dual-color femtosecond laser pulses in fused silica

2021 ◽  
Author(s):  
Saba Zafar ◽  
Dong-Wei Li ◽  
Acner Camino ◽  
Jun-Wei Chang ◽  
Zuo-Qiang Hao
Keyword(s):  
Femtosecond Laser ◽  
High Power ◽  
Microlens Array ◽  
Laser Pulses ◽  
Femtosecond Laser Pulses ◽  
Fused Silica ◽  
Spectral Energy ◽  
Phase Matching ◽  
Fundamental Wavelength ◽  
Fundamental Laser

Abstract High power supercontinuum (SC) is generated by focusing 800 nm and 400 nm femtosecond laser pulses in fused silica with a microlens array. It is found that the spectrum of the SC is getting broader compared with the case of single laser pulse, and the spectral energy density between the two fundamental laser wavelengths is getting significantly higher by optimizing the phase matching angle of the BBO. It exceeds μJ/nm over 490 nm range which is from 380 nm to 870 nm, overcoming the disadvantage of relative lower power in the ranges far from fundamental wavelength.

Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost

2018 ◽  
Vol 2018 (1) ◽  
pp. 000037-000042
Author(s):  
Henning Hübner ◽  
Christian Ohde ◽  
Dirk Ruess
Keyword(s):  
Large Scale ◽  
Metal Deposition ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Process Technology ◽  
Process Step ◽  
Glass Substrates ◽  
Component Design ◽  
Advanced Packaging

Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.

scholarly journals Fabrication of Multiscale-Structure Wafer-Level Microlens Array Mold

2019 ◽  
Vol 9 (3) ◽  
pp. 487 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Xiaoxiao Wei
Keyword(s):  
Low Cost ◽  
Form Factors ◽  
Cost Effective ◽  
Microlens Array ◽  
Practical Method ◽  
Reduced Form ◽  
Wafer Level ◽  
Polycrystalline Aluminum ◽  
Microlens Arrays ◽  
Multiscale Structure

The design and manufacture of cost-effective miniaturized optics at wafer level, usingadvanced semiconductor-like techniques, enables the production of reduced form-factor cameramodules for optical devices. However, suppressing the Fresnel reflection of wafer-level microlensesis a major challenge. Moth-eye nanostructures not only satisfy the antireflection requirementof microlens arrays, but also overcome the problem of coating fracture. This novel fabricationprocess, based on a precision wafer-level microlens array mold, is designed to meet the demandfor small form factors, high resolution, and cost effectiveness. In this study, three different kinds ofaluminum material, namely 6061-T6 aluminum alloy, high-purity polycrystalline aluminum, and purenanocrystalline aluminum were used to fabricate microlens array molds with uniform nanostructures.Of these three materials, the pure nanocrystalline aluminum microlens array mold exhibited auniform nanostructure and met the optical requirements. This study lays a solid foundation for theindustrial acceptation of novel and functional multiscale-structure wafer-level microlens arrays andprovides a practical method for the low-cost manufacture of large, high-quality wafer-level molds.

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

2013 ◽  
Vol 60 ◽  
pp. 251-259 ◽  
Author(s):  
Fredrik Forsberg ◽  
Niclas Roxhed ◽  
Andreas C. Fischer ◽  
Björn Samel ◽  
Per Ericsson ◽  
...  
Keyword(s):  
Focal Plane ◽  
Large Scale ◽  
Vacuum Packaging ◽  
Focal Plane Arrays ◽  
Heterogeneous Integration ◽  
Wafer Level

scholarly journals Design and Fabrication of Wafer-Level Microlens Array with Moth-Eye Antireflective Nanostructures

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 747 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Bo Yang ◽  
Wei Zhang ◽  
Xiaoxiao Wei ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Production Efficiency ◽  
Low Cost ◽  
Microlens Array ◽  
Wafer Level ◽  
Lens Array ◽  
Wafer Level Packaging ◽  
High Production ◽  
Aspherical Lenses ◽  
Profile Accuracy

Wafer-level packaging (WLP) based camera module production has attracted widespread industrial interest because it offers high production efficiency and compact modules. However, suppressing the surface Fresnel reflection losses is challenging for wafer-level microlens arrays. Traditional dielectric antireflection (AR) coatings can cause wafer warpage and coating fractures during wafer lens coating and reflow. In this paper, we present the fabrication of a multiscale functional structure-based wafer-level lens array incorporating moth-eye nanostructures for AR effects, hundred-micrometer-level aspherical lenses for camera imaging, and a wafer-level substrate for wafer assembly. The proposed fabrication process includes manufacturing a wafer lens array metal mold using ultraprecise machining, chemically generating a nanopore array layer, and replicating the multiscale wafer lens array using ultraviolet nanoimprint lithography. A 50-mm-diameter wafer lens array is fabricated containing 437 accurate aspherical microlenses with diameters of 1.0 mm; each lens surface possesses nanostructures with an average period of ~120 nm. The microlens quality is sufficient for imaging in terms of profile accuracy and roughness. Compared to lenses without AR nanostructures, the transmittance of the fabricated multiscale lens is increased by ~3% under wavelengths of 400–750 nm. This research provides a foundation for the high-throughput and low-cost industrial application of wafer-level arrays with AR nanostructures.

scholarly journals Batch Fabrication of Silicon Nanometer Tip Using Isotropic Inductively Coupled Plasma Etching

Micromachines ◽  
2020 ◽  
Vol 11 (7) ◽  
pp. 638
Author(s):  
Lihao Wang ◽  
Meijie Liu ◽  
Junyuan Zhao ◽  
Jicong Zhao ◽  
Yinfang Zhu ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Inductively Coupled Plasma ◽  
Large Scale ◽  
Etch Depth ◽  
Wafer Level ◽  
Small Surface ◽  
Inductively Coupled Plasma Etching ◽  
Inductively Coupled ◽  
Icp Etching ◽  
Batch Fabrication

This work reports a batch fabrication process for silicon nanometer tip based on isotropic inductively coupled plasma (ICP) etching technology. The silicon tips with nanometer apex and small surface roughness are produced at wafer-level with good etching homogeneity and repeatability. An ICP etching routine is developed to make silicon tips with apex radius less than 5 nm, aspect ratio greater than 5 at a tip height of 200 nm, and tip height more than 10 μm, and high fabrication yield is achieved by mask compensation and precisely controlling lateral etch depth, which is significant for large-scale manufacturing.

Large-Scale Synthesis and Systematic Photoluminescence Properties of Monolayer MoS2 on Fused Silica

2016 ◽  
Vol 8 (28) ◽  
pp. 18570-18576 ◽  
Author(s):  
Yi Wan ◽  
Hui Zhang ◽  
Kun Zhang ◽  
Yilun Wang ◽  
Bowen Sheng ◽  
...  
Keyword(s):  
Large Scale ◽  
Fused Silica ◽  
Monolayer Mos2 ◽  
Photoluminescence Properties ◽  
Large Scale Synthesis
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