Plasma-etching-induced oxide degradation: effects upon device performance and circuit yield

1996 ◽  
Author(s):  
Scott T. Martin ◽  
Guann-pyng Li ◽  
Eugene Worley ◽  
Joe White
Keyword(s):  
Plasma Etching ◽  
Device Performance ◽  
Oxide Degradation ◽  
Circuit Yield

The effects of plasma etching induced gate oxide degradation on MOSFET's 1/f noise

1995 ◽  
Vol 16 (2) ◽  
pp. 61-63 ◽  
Author(s):  
Chun Hu ◽  
Ji Zhao ◽  
G.P. Li ◽  
P. Liu ◽  
E. Worley ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Gate Oxide ◽  
Oxide Degradation

Tuning the thickness of black phosphorus via ion bombardment-free plasma etching for device performance improvement

2016 ◽  
Vol 4 (26) ◽  
pp. 6234-6239 ◽  
Author(s):  
Geonyeop Lee ◽  
Jong-Young Lee ◽  
Gwan-Hyoung Lee ◽  
Jihyun Kim
Keyword(s):  
Performance Improvement ◽  
Plasma Etching ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Ion Bombardment ◽  
Black Phosphorus ◽  
Device Performance ◽  
Free Plasma

Field-effect transistors based on thickness-controlled black phosphorus showed improved device performances after ion bombardment-free plasma etching.

Effects of plasma-etching-induced gate oxide degradation on MOSFET's 1/f noise

1994 ◽  
Author(s):  
Chun Hu ◽  
Scott T. Martin ◽  
Eugene Worley ◽  
Joe White ◽  
Ray Kjar ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Gate Oxide ◽  
Oxide Degradation

Particle characterization of CVD tungsten metallization for 64 MBIT DRAM

1991 ◽  
Vol 49 ◽  
pp. 896-897
Author(s):  
Marylyn Bennett-Lilley ◽  
Thomas T.H. Fu ◽  
David D. Yin ◽  
R. Allen Bowling
Keyword(s):  
Chemical Vapor ◽  
Device Performance ◽  
Particle Characterization ◽  
Particle Generation ◽  
Tungsten Hexafluoride ◽  
Homogeneous Particle ◽  
Multiple Levels ◽  
Circuit Density ◽  
Sources Of Contamination

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

1996 ◽  
Vol 54 ◽  
pp. 944-945
Author(s):  
Richard G. Sartore
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Microwave Integrated Circuits ◽  
Monolithic Microwave Integrated Circuits ◽  
Thick Gold ◽  
Gaas Devices ◽  
Source Distance ◽  
Margin Of Error ◽  
Dimensional Measurements ◽  
Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

Charging microscopy and cathodoluminescence imaging of semi-insulating gallium arsenide

1986 ◽  
Vol 44 ◽  
pp. 816-817
Author(s):  
T.C. Sheu ◽  
S. Myhajlenko ◽  
D. Davito ◽  
J.L. Edwards ◽  
R. Roedel ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Secondary Electron ◽  
Crystal Defects ◽  
Device Performance ◽  
Gaas Wafer ◽  
Surface Charging ◽  
Gaas Substrates ◽  
Voltage Contrast ◽  
Cathodoluminescence Imaging ◽  
Scanning Electron

Liquid encapsulated Czochralski (LEC) semi-insulating (SI) GaAs has applications in integrated optics and integrated circuits. Yield and device performance is dependent on the homogeniety of the wafers. Therefore, it is important to characterise the uniformity of the GaAs substrates. In this respect, cathodoluminescence (CL) has been used to detect the presence of crystal defects and growth striations. However, when SI GaAs is examined in a scanning electron microscope (SEM), there will be a tendency for the surface to charge up. The surface charging affects the backscattered and secondary electron (SE) yield. Local variations in the surface charge will give rise to contrast (effectively voltage contrast) in the SE image. This may be associated with non-uniformities in the spatial distribution of resistivity. Wakefield et al have made use of “charging microscopy” to reveal resistivity variations across a SI GaAs wafer. In this work we report on CL imaging, the conditions used to obtain “charged” SE images and some aspects of the contrast behaviour.

Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study

1990 ◽  
Vol 48 (4) ◽  
pp. 566-567
Author(s):  
F. Banhart ◽  
F.O. Phillipp ◽  
R. Bergmann ◽  
E. Czech ◽  
M. Konuma ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Liquid Phase ◽  
Plasma Etching ◽  
Liquid Phase Epitaxy ◽  
Three Dimensional ◽  
Microscopical Study ◽  
Sample Temperature ◽  
Structural Defects ◽  
Si Substrates ◽  
Etched Surface

Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

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