Line end shortening and iso-dense etch bias improvement by ALD spacer shrink process

2017 ◽  
Author(s):  
Rui Chen ◽  
Granger Lobb ◽  
Aleksandra Clancy ◽  
Bradley Morgenfeld ◽  
Shyam Pal
Keyword(s):  
Etch Bias

Machine Learning Models for Edge Placement Error Based Etch Bias

2020 ◽  
pp. 1-1
Author(s):  
Yang Meng ◽  
Young-Chang Kim ◽  
Shujie Guo ◽  
Zhongli Shu ◽  
Yingchun Zhang ◽  
...  
Keyword(s):  
Machine Learning ◽  
Learning Models ◽  
Etch Bias ◽  
Machine Learning Models

Approaching zero etch bias at Cr etch process

2005 ◽  
Author(s):  
Pavel Nesladek ◽  
Norbert Falk ◽  
Andreas Wiswesser ◽  
Renee Koch ◽  
Björn Sass
Keyword(s):  
Etch Bias

Study of model based etch bias retarget for OPC

2010 ◽  
Author(s):  
Qingwei Liu ◽  
Renqiang Cheng ◽  
Liguo Zhang
Keyword(s):  
Model Based ◽  
Etch Bias

Photoreflectance Characterisation of Reactive Ion Etched Silicon

1993 ◽  
Vol 324 ◽  
Author(s):  
M. Murtagh ◽  
J. T. Beechinor ◽  
P. A. F. Herbert ◽  
P.V. Kelly ◽  
G. M. Crean ◽  
...  
Keyword(s):  
Etch Rate ◽  
Room Temperature ◽  
Rutherford Backscattering Spectrometry ◽  
Applied Bias ◽  
Plasma Surface ◽  
Rate Analysis ◽  
Etched Silicon ◽  
P Type ◽  
Etch Bias

AbstractReactive ion etching (RIE) of p-type 2-3 †cm resistivity silicon (100) was characterised using Photoreflectance (PR), Rutherford Backscattering Spectrometry (RBS) and Spectroscopic Ellipsometry (SE). Isochronal (5 minutes) etching was performed at various DC etch biases (0-500V) using a SiCl4 etch chemistry. The substrate etch rate dependence on applied bias was determined using mechanical profilometry. A distinct shift in the A3–A1 Si transition and significant spectral broadening of the room temperature PR spectra was observed as a function of etch bias. Photoreflectance results are correlated with RBS, SE and etch rate analysis. It is demonstrated that the PR spectra reflect a complex, competitive, plasma-surface interaction during the RIE process.

Improvements in Polysilicon Etch Bias and Transistor Gate Control With Module Level APC Methodologies

2005 ◽  
Vol 18 (4) ◽  
pp. 522-527 ◽  
Author(s):  
D.A. Williams ◽  
A.R. Locander ◽  
T. Herrera ◽  
J.D. Garza ◽  
C.K. Parker
Keyword(s):  
Gate Control ◽  
Etch Bias
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