Improved performance and stability of In-Sn-Zn-O thin film transistor by introducing a meso-crystalline ZrO2 high-k gate insulator

2019 ◽  
Vol 37 (2) ◽  
pp. 020924 ◽  
Author(s):  
Wan-Ho Choi ◽  
Jiazhen Sheng ◽  
Hyun-Jun Jeong ◽  
Jin-Seong Park ◽  
MinJung Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
High K ◽  
Improved Performance

scholarly journals Performance Enhancement of Pentacene-Based Organic Thin-Film Transistors Using a High-K PVA/Low-K PVP Bilayer as the Gate Insulator

Polymers ◽  
2021 ◽  
Vol 13 (22) ◽  
pp. 3941
Author(s):  
Ching-Lin Fan ◽  
Hou-Yen Tsao ◽  
Yu-Shien Shiah ◽  
Che-Wei Yao ◽  
Po-Wei Cheng
Keyword(s):  
Thin Film ◽  
Performance Enhancement ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Control Sample ◽  
Drain Current ◽  
Gate Insulator ◽  
Organic Thin Film ◽  
High K ◽  
Low K

In this study, we proposed using the high-K polyvinyl alcohol (PVA)/low-K poly-4-vinylphenol (PVP) bilayer structure as the gate insulator to improve the performance of a pentacene-based organic thin-film transistor. The dielectric constant of the optimal high-K PVA/low-K PVP bilayer was 5.6, which was higher than that of the single PVP layer. It resulted in an increase in the gate capacitance and an increased drain current. The surface morphology of the bilayer gate dielectric could be suitable for pentacene grain growth because the PVP layer was deposited above the organic PVA surface, thereby replacing the inorganic surface of the ITO gate electrode. The device performances were significantly improved by using the bilayer gate dielectric based upon the high-K characteristics of the PVA layer and the enlargement of the pentacene grain. Notably, the field-effect mobility was increased from 0.16 to 1.12 cm2/(Vs), 7 times higher than that of the control sample.

Improvement of Amorphous InGaZnO Thin-Film Transistor Using High-k SrTa2 O6 as Gate Insulator Deposited by Sputtering Method

2018 ◽  
Vol 216 (5) ◽  
pp. 1700773 ◽  
Author(s):  
Takanori Takahashi ◽  
Takeshi Hoga ◽  
Ryoko Miyanaga ◽  
Kento Oikawa ◽  
Mami N. Fujii ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
High K ◽  
Amorphous Ingazno

Room temperature fabricated ZnO thin film transistor using high-K Bi1.5Zn1.0Nb1.5O7 gate insulator prepared by sputtering

2006 ◽  
Vol 89 (2) ◽  
pp. 022905 ◽  
Author(s):  
Il-Doo Kim ◽  
Mi-Hwa Lim ◽  
KyongTae Kang ◽  
Ho-Gi Kim ◽  
Si-Young Choi
Keyword(s):  
Thin Film ◽  
Room Temperature ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
Zno Thin Film ◽  
High K

High k PVP titanium dioxide composite dielectric with low leakage current for thin film transistor

2021 ◽  
pp. 106413
Author(s):  
Yuexin Yang ◽  
Zhuohui Xu ◽  
Tian Qiu ◽  
Honglong Ning ◽  
Jinyao Zhong ◽  
...  
Keyword(s):  
Thin Film ◽  
Titanium Dioxide ◽  
Leakage Current ◽  
Thin Film Transistor ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K

The improved performance of a transparent ZnO thin-film transistor with AlN/Al2O3double gate dielectrics

2009 ◽  
Vol 24 (5) ◽  
pp. 055008 ◽  
Author(s):  
Jung-Min Lee ◽  
Byung-Hyun Choi ◽  
Mi-Jung Ji ◽  
Jung-Ho Park ◽  
Jae-Hong Kwon ◽  
...  
Keyword(s):  
Thin Film ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Zno Thin Film ◽  
Improved Performance

scholarly journals Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

2019 ◽  
Vol 35 (2) ◽  
Author(s):  
Bui Nguyen Quoc Trinh
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Gate Insulator ◽  
Current Ratio ◽  
Memory State ◽  
Small Loss ◽  
Memory Circuit ◽  
Novel Concept ◽  
Data Reading

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi3.25La0.75Ti3O12 and PbZr0.52TiO0.48O3 (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle. Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

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