Enhanced wall-plug efficiency in monolithically integrated vertical light-emitting-diode cells based on III-nitride heterostructures

Author(s):  
Hyung Jo Park ◽  
Hyo Jung Bae ◽  
Jun Beom Park ◽  
Jun Seok Ha ◽  
Tak Jeong ◽  
...  
Nano Letters ◽  
2011 ◽  
Vol 11 (2) ◽  
pp. 385-390 ◽  
Author(s):  
Linus C. Chuang ◽  
Forrest G. Sedgwick ◽  
Roger Chen ◽  
Wai Son Ko ◽  
Michael Moewe ◽  
...  

2016 ◽  
Author(s):  
Renjie Wang ◽  
Yong-Ho Ra ◽  
Yuanpeng Wu ◽  
Songrui Zhao ◽  
Hieu P. T. Nguyen ◽  
...  

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Keundong Lee ◽  
Dongha Yoo ◽  
Hongseok Oh ◽  
Gyu-Chul Yi

AbstractWe report flexible and monolithically integrated multicolor light-emitting diode (LED) arrays using morphology-controlled growth of GaN microstructures on chemical-vapor-deposited (CVD) graphene films. As the morphology-controlled growth template of GaN microstructures, we used position-controlled ZnO nanostructure arrays with different spacings grown on graphene substrates. In particular, we investigated the effect of the growth parameters, including micropattern spacings and growth time and temperature, on the morphology of the GaN microstructures when they were coated on ZnO nanostructures on graphene substrates. By optimizing the growth parameters, both GaN microrods and micropyramids formed simultaneously on the graphene substrates. Subsequent depositions of InGaN/GaN quantum well and p-GaN layers and n- and p-type metallization yielded monolithic integration of microstructural LED arrays on the same substrate, which enabled multicolor emission depending on the shape of the microstructures. Furthermore, the CVD graphene substrates beneath the microstructure LEDs facilitated transfer of the LED arrays onto any foreign substrate. In this study, Cu foil was used for flexible LEDs. The flexible devices exhibited stable electroluminescence, even under severe bending conditions. Cyclic bending tests demonstrated the excellent mechanical stability and reliability of the devices.


2020 ◽  
Vol 11 (1) ◽  
Author(s):  
Svenja Mauthe ◽  
Yannick Baumgartner ◽  
Marilyne Sousa ◽  
Qian Ding ◽  
Marta D. Rossell ◽  
...  

Abstract Direct epitaxial growth of III-Vs on silicon for optical emitters and detectors is an elusive goal. Nanowires enable the local integration of high-quality III-V material, but advanced devices are hampered by their high-aspect ratio vertical geometry. Here, we demonstrate the in-plane monolithic integration of an InGaAs nanostructure p-i-n photodetector on Si. Using free space coupling, photodetectors demonstrate a spectral response from 1200-1700 nm. The 60 nm thin devices, with footprints as low as ~0.06 μm2, provide an ultra-low capacitance which is key for high-speed operation. We demonstrate high-speed optical data reception with a nanostructure photodetector at 32 Gb s−1, enabled by a 3 dB bandwidth exceeding ~25 GHz. When operated as light emitting diode, the p-i-n devices emit around 1600 nm, paving the way for future fully integrated optical links.


2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
Huamao Huang ◽  
Jinyong Hu ◽  
Hong Wang

Three-dimensional (3D) backside reflector, compared with flat reflectors, can improve the probability of finding the escape cone for reflecting lights and thus enhance the light-extraction efficiency (LEE) for GaN-based light-emitting diode (LED) chips. A triangle-lattice of microscale SiO2cone array followed by a 16-pair Ti3O5/SiO2distributed Bragg reflector (16-DBR) was proposed to be attached on the backside of sapphire substrate, and the light-output enhancement was demonstrated by numerical simulation and experiments. The LED chips with flat reflectors or 3D reflectors were simulated using Monte Carlo ray tracing method. It is shown that the LEE increases as the reflectivity of backside reflector increases, and the light-output can be significantly improved by 3D reflectors compared to flat counterparts. It can also be observed that the LEE decreases as the refractive index of the cone material increases. The 3D 16-DBR patterned by microscale SiO2cone array benefits large enhancement of LEE. This microscale pattern was prepared by standard photolithography and wet-etching technique. Measurement results show that the 3D 16-DBR can provide 12.1% enhancement of wall-plug efficiency, which is consistent with the simulated value of 11.73% for the enhancement of LEE.


2014 ◽  
Vol 22 (S7) ◽  
pp. A1768 ◽  
Author(s):  
Renjie Wang ◽  
Hieu P. T. Nguyen ◽  
Ashfiqua T. Connie ◽  
J. Lee ◽  
Ishiang Shih ◽  
...  

2004 ◽  
Vol 84 (13) ◽  
pp. 2253-2255 ◽  
Author(s):  
H. W. Choi ◽  
C. Liu ◽  
E. Gu ◽  
G. McConnell ◽  
J. M. Girkin ◽  
...  

2016 ◽  
Vol 109 (19) ◽  
pp. 191104 ◽  
Author(s):  
B. P. Yonkee ◽  
E. C. Young ◽  
S. P. DenBaars ◽  
S. Nakamura ◽  
J. S. Speck

Sign in / Sign up

Export Citation Format

Share Document