Variation in the threshold voltage of amorphous-In2Ga2ZnO7 thin-film transistors by ultrathin Al2O3 passivation layer

2013 ◽  
Vol 31 (6) ◽  
pp. 061205 ◽  
Author(s):  
Sang Ho Rha ◽  
Un Ki Kim ◽  
Jisim Jung ◽  
Eun Suk Hwang ◽  
Seung Jun Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Passivation Layer

Stability of Organic Thin Film Transistors

2004 ◽  
Vol 814 ◽  
Author(s):  
Jeong In Han ◽  
Yong Hoon Kim ◽  
Sung Kyu Park ◽  
Dae Gyu Moon ◽  
Won Keun Kim
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Organic Thin Film Transistors ◽  
Passivation Layer ◽  
Organic Thin Film ◽  
Field Effect Mobility ◽  
Saturation Field ◽  
The Stability

AbstractThe stability of organic thin film transistors (OTFTs) has become one of the most vital issues in this area of research. In this report, we investigated the stability of rubber stamp printed OTFTs. The electrical properties such as saturation field effect mobility, threshold voltage and on/off current ratio change significantly in ambient air condition. In order to analyze the degradation of the device, transistors were measured in vacuum, dry N2 and air environment as a function of time. In vacuum and dry N2 atmosphere, saturation field effect mobility and threshold voltage variations are relatively small compared to those measured in ambient condition.To realize an air stable device, we applied a passivation layer which protects the device from oxygen or water molecules which is believed to be the source of the degradation. With the passivation layer, the threshold voltage shift was reduced suggesting that a proper passivation layer is a prerequisite in organic-based electronics.

scholarly journals Enhancement of Electrical Characteristics and Stability of Amorphous Si-Sn-O Thin Film Transistors with SiOx Passivation Layer

Materials ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 1440 ◽  
Author(s):  
Xianzhe Liu ◽  
Weijing Wu ◽  
Weifeng Chen ◽  
Honglong Ning ◽  
Xiaochen Zhang ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
Passivation Layer ◽  
Device Performance ◽  
Electrical Characteristics ◽  
Initial State ◽  
Large Size ◽  
Amorphous Si

In this research, a passivated methodology was proposed for achieving good electrical characteristics for back-channel-etch (BCE) typed amorphous Si-Sn-O thin film transistors (a-STO TFTs). This methodology implied that the thermal annealing (i.e., pre-annealing) should be carried out before deposition of a SiOx passivation layer. The pre-annealing played an important role in affecting device performance, which did get rid of the contamination of the lithography process. Simultaneously, the acceptor-like sub-gap density of states (DOS) of devices was extracted for further understanding the reason for improving device performance. It found that the SiOx layer could reduce DOS of the device and successfully protect the device from surroundings. Finally, a-STO TFT applied with this passivated methodology could possess good electrical properties including a saturation mobility of 4.2 ± 0.2 cm2/V s, a low threshold voltage of 0.00 V, a large on/off current ratio of 6.94 × 108, and a steep subthreshold swing of 0.23 V/decade. The threshold voltage slightly shifted under bias stresses and recovered itself to its initial state without any annealing procedure, which was attributed to the charge trapping in the bulk dielectric layers or interface. The results of this study indicate that a-STO TFT could be a robust candidate for realizing a large-size and high-resolution display.

Cyanophenoxy-Substituted Silicon Phthalocyanines for Low Threshold Voltage n-Type Organic Thin-Film Transistors

2021 ◽  
Author(s):  
Benjamin King ◽  
Andrew J. Daszczynski ◽  
Nicole A. Rice ◽  
Alexander J. Peltekoff ◽  
Nathan J. Yutronkie ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Silicon Phthalocyanines ◽  
Low Threshold

scholarly journals Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 327
Author(s):  
Je-Hyuk Kim ◽  
Jun Tae Jang ◽  
Jong-Ho Bae ◽  
Sung-Jin Choi ◽  
Dong Myong Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Oxygen Content ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electron Trapping ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Drain Side ◽  
Bottom Gate

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Threshold voltage of excimer-laser-annealed polycrystalline silicon thin-film transistors

2000 ◽  
Vol 76 (17) ◽  
pp. 2442-2444 ◽  
Author(s):  
C. T. Angelis ◽  
C. A. Dimitriadis ◽  
F. V. Farmakis ◽  
J. Brini ◽  
G. Kamarinos ◽  
...  
Keyword(s):  
Thin Film ◽  
Excimer Laser ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film

Interface Engineering for Precise Threshold Voltage Control in Multilayer-Channel Thin Film Transistors

2016 ◽  
Vol 3 (24) ◽  
pp. 1600713 ◽  
Author(s):  
Ji Hoon Park ◽  
Fwzah H. Alshammari ◽  
Zhenwei Wang ◽  
Husam N. Alshareef
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Voltage Control ◽  
Interface Engineering

Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

2013 ◽  
Vol 103 (20) ◽  
pp. 203501 ◽  
Author(s):  
Uio-Pu Chiou ◽  
Jia-Min Shieh ◽  
Chih-Chao Yang ◽  
Wen-Hsien Huang ◽  
Yo-Tsung Kao ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Metal Gate ◽  
Si Thin Film ◽  
Nanocrystalline Si

Mechanisms for Defect Creation and Removal in Hydrogenated and Deuterated Amorphous Silicon Studied using Thin Film Transistors

2006 ◽  
Vol 910 ◽  
Author(s):  
Andew Flewitt ◽  
Shufan Lin ◽  
William I Milne ◽  
Ralf B Wehrspohn ◽  
Martin J Powell
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Elevated Temperatures ◽  
Chemical Vapour ◽  
Rf Plasma ◽  
Gate Bias ◽  
Removal Process ◽  
Defect Creation

AbstractIt has been widely observed that thin film transistors (TFTs) incorporating an hydrogenated amorphous silicon (a-Si:H) channel exhibit a progressive shift in their threshold voltage with time upon application of a gate bias. This is attributed to the creation of metastable defects in the a-Si:H which can be removed by annealing the device at elevated temperatures with no bias applied to the gate, causing the threshold voltage to return to its original value. In this work, the defect creation and removal process has been investigated using both fully hydrogenated and fully deuterated amorphous silicon (a-Si:D) TFTs. In both cases, material was deposited by rf plasma enhanced chemical vapour deposition over a range of gas pressures to cover the a-g transition. The variation in threshold voltage as a function of gate bias stressing time, and annealing time with no gate bias, was measured. Using the thermalisation energy concept, it has been possible to quantitatively determine the distribution of energies required for defect creation and removal as well as the associated attempt-to-escape frequencies. The defect creation and removal process in a-Si:H is then discussed in the light of these results.

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