Scanned-spot-array extreme ultraviolet imaging for high-volume maskless lithography

2012 ◽  
Vol 30 (5) ◽  
pp. 051606 ◽  
Author(s):  
Kenneth C. Johnson
Keyword(s):  
Extreme Ultraviolet ◽  
High Volume ◽  
Maskless Lithography ◽  
Spot Array

ITRS lithography roadmap: 2015 challenges

2015 ◽  
Vol 4 (4) ◽  
Author(s):  
Mark Neisser ◽  
Stefan Wurm
Keyword(s):  
Self Assembly ◽  
Lower Cost ◽  
Extreme Ultraviolet ◽  
Cost Effective ◽  
High Volume ◽  
Time Frame ◽  
Maskless Lithography ◽  
Euv Lithography ◽  
Improved Performance ◽  
Better Than

AbstractIn the past few years, novel methods of patterning have made considerable progress. In 2011, extreme ultraviolet (EUV) lithography was the front runner to succeed optical lithography. However, although EUV tools for pilot production capability have been installed, its high volume manufacturing (HVM) readiness continues to be gated by productivity and availability improvements taking longer than expected. In the same time frame, alternative and/or complementary technologies to EUV have made progress. Directed self-assembly (DSA) has demonstrated improved defectivity and progress in integration with design and pattern process flows. Nanoimprint improved performance considerably and is pilot production capable for memory products. Maskless lithography has made progress in tool development and could have an α tool ready in the late 2015 or early 2016. But they all have to compete with multiple patterning. Quadruple patterning is already demonstrated and can pattern lines and spaces down to close to 10-nm half pitch. The other techniques have to do something better than quadruple patterning does to be chosen for implementation. DSA and NIL promise a lower cost. EUV promises a simpler and shorter process and the creation of 2-D patterns more easily with much reduced complexity compared to multiple patterning. Maskless lithography promises to make chip personalization easy and to be particularly cost effective for low-volume chip designs. Decision dates for all of the technologies are this year or next year.

Development of element technologies for EUVL

2015 ◽  
Vol 4 (4) ◽  
Author(s):  
Hiroo Kinoshita ◽  
Takeo Watanabe ◽  
Tetsuo Harada
Keyword(s):  
Extreme Ultraviolet ◽  
Random Access ◽  
High Volume ◽  
Development Stage ◽  
Extreme Ultraviolet Lithography ◽  
Applied Physics ◽  
Reflectivity Measurement ◽  
Ultraviolet Lithography ◽  
Mask Inspection ◽  
The University

AbstractThirty years have passed since the first report on extreme ultraviolet lithography (EUVL) was presented at the annual meeting of the Japanese Society of Applied Physics in 1986. This technology is now in the manufacturing development stage. The high-volume manufacturing of dynamic-random-access-memory (DRAM) chips with a line width of 15 nm is expected in 2016. However, there are critical development issues that remain: generating a stand-alone EUV source with a higher power and producing a mask inspection tool for obtaining zero-defect masks. The Center for EUVL at the University of Hyogo was established in 2010. At present, it utilizes various types of equipment, such as an EUV mask defect inspection tool, an interference-lithography system, a device for measuring the thickness of carbon contamination film deposited by resist outgassing, and reflectivity measurement systems.

Parallel micro manipulator for optical spot array alignment of maskless lithography

2015 ◽  
Vol 21 (12) ◽  
pp. 2663-2668
Author(s):  
Zheng Yuan Li ◽  
Jong Yoon Choi ◽  
Yong Seok Ihn ◽  
Sang-Hoon Ji ◽  
Ja Choon Koo
Keyword(s):  
Maskless Lithography ◽  
Micro Manipulator ◽  
Spot Array

scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Parallel Micro Manipulator for Effective Optical Spot Array Alignment

2014 ◽  
Author(s):  
Zheng Yuan Li ◽  
Sae Whan Park ◽  
Yong Seok Inh ◽  
Jong Yoon Choi ◽  
Ja Choon Koo
Keyword(s):  
Genetic Algorithm ◽  
Parallel Manipulator ◽  
Experimental Result ◽  
Kinematic Characteristic ◽  
Maskless Lithography ◽  
Nano Fabrication ◽  
Micro Manipulator ◽  
Spot Array ◽  
Exposure Process ◽  
Lithography Technology

Photolithography is one of the core technologies of micro-nano fabrication. Recently, lithography technology is applied to diverse field of technologies. These technologies include MEMS (micro electro mechanical system) devices, FPD (flat panel display), and semiconductor industry. When it comes to the typical exposure process of lithography technology, photomask costs is occupying large portion of the optical system. So, how to reduce the cost of the mask and employing maskless lithography technology has become an important issue to engineers. Although there being both advantages and disadvantages, maskless lithography is a receiving substantial attention from engineers in the fileds of micro-nano fabrication. With the development of technology, low cost, flexibility, efficiency in the fabrication of device are in high demand in maskless lithography technology. How to generate line/space patterns is gaining considerable attention in terms of maskless lithography exposure process. In order to achieve the accurate alignments of numerous optical heads within a reasonable amount of tack time, installing autonomous position align micro parallel manipulator system in each optical heads required. Applied parallel manipulator that consists of four 2-DOF (degree of freedom) decoupled actuator gives chances to provide 6-DOF independence motion, and has strength in high accuracy. It is thus, this parallel manipulator is suitable for the experiment. This paper covers the follows: First, we reported the DMD (Digital Micro mirror Device)-based makless lithography system to introduce spot array method in maskless digital exposure process. Second, applying a redundant parallel micro manipulator and analyzing kinematic characteristic of the 4-[PP]PS parallel manipulator is described. After that, comparing benefits and drawbacks of 4-[PP]PS parallel and 4-DOF serial manipulator is covered. Third, proposing a suitable error model of the system and applying the genetic algorithm to alignment spot array concerning position correction. Finally, we designed experiment which has vision sensor and align unit to verify positioning algorithm. Simulation and experimental result will be shown with the regard to parallel manipulator can find the optimal solution based on genetic algorithm and carry out the problem of spot array alignment by reducing the position error of the system.

Optical Head Alignment Method Using Serial Manipulators for Maskless Lithography System

2014 ◽  
Author(s):  
Jong Yoon Choi ◽  
Sae Whan Park ◽  
Yong Seok Inh ◽  
Zheng Yuan Li ◽  
Ja Choon Koo
Keyword(s):  
Optical System ◽  
Cost Efficiency ◽  
Fitness Function ◽  
Alignment Algorithm ◽  
Maskless Lithography ◽  
Test Bed ◽  
Unit Scale ◽  
Lithography System ◽  
Spot Array ◽  
Lithography Technology

As the cost of photo masks for display panel is very high, researchers have been developing maskless lithography using electron beam in this system. However the maskless lithography system has typical drawback in some respects. These issues include productivity, size of the system and cost efficiency. To cope with these problems, take reflectance rate and position of spot array into consideration is required. The lithography technology has been focused on studying both reflectance of light from DMDs (digital micromirror devices) and the position of generated spot array. As the lithography technology has been developed steadily, there exists plenty type of maskless lithography nowadays. DMD-based optical maskless lithography system is gaining substantial attention from researchers and engineers for its outstanding performance concerning cost efficiency and high throughput. Also, accurate alignment of spot array is on requisition under the condition of micro-unit scale. As a result, the maskless lithography system is faced with the problem relevant to accurate alignment. For instance, the actual alignment of spot array has been done by hand although it has a chance to show deleterious effects on productivity. In this paper, an alignment algorithm was suggested for the purpose of satisfying generation of accurate alignment of spot array. The algorithm is based on concerning kinematics of maskless lithography system. Thus, the suggested algorithm enable to reducing the error that has been measured from the spot array. Defining spot array error that is fitness function of genetic algorithm is introduced at first. An alignment algorithm that has correlation with kinematics of the optical system and spot array error will be represented in sequence. After that, designing 4 DOF align unit will be covered in kinematics analysis chapter. Finally, designing test bed of optical system using vision sensor and align unit is considered in order to validate the suggested alignment algorithm with experiment.

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