scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Increased High-Temperature Reliability and Package Hardening of Commercial Integrated Circuits (Through Die Extraction, Electroless Nickel/Gold Pad Reconditioning, and Ceramic Re-Assembly)

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000123-000128
Author(s):  
Erick M. Spory
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Value Added ◽  
Electroless Nickel ◽  
High Volume ◽  
Gold Plating ◽  
Global Circuit ◽  
Temperature Applications

There is an ever-increasing demand for electronics in higher temperature applications, both in variety and volume. In many cases, the actual integrated circuit within the plastic packaging can support operation at higher temperatures, although the packaging and connectivity is unable to do so. Ultimately, there still remains a significant gap in the volume demand required for high temperature integrated circuit lines to justify support of more expensive ceramic solutions by the original component manufacturer vs. the cheaper, high-volume PEM flows. Global Circuit Innovations, Inc. has developed a manufacturable, cost-effective solution to extract the integrated circuit from any plastic encapsulated device and subsequently re-package that device into an identical ceramic footprint, with the ability to maintain high-integrity connectivity to the device and enabling functionality for 1000's of hours at temperatures at 250C and beyond. This process represents a high-value added solution to provide high-temperature integrated circuits for a large spectrum of requirements: low-volume, quick-turn evaluation of integrated circuit prototyping, as well as medium to high-volume production needs for ongoing production needs. Although both die extraction and integrated circuit pad electroless nickel/gold plating have both been performed successfully for many years in the semiconductor industry, Global Circuit Innovations, Inc. has been able to combine the two in a reliable, volume manufacturing flow to satisfy many of the stringent requirements for high-temperature applications.

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

scholarly journals Miniaturization of CMOS

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 293 ◽  
Author(s):  
Henry H. Radamson ◽  
Xiaobin He ◽  
Qingzhu Zhang ◽  
Jinbiao Liu ◽  
Hushan Cui ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Strain Engineering ◽  
Transistor Structure ◽  
Technology Roadmap ◽  
Effect Transistor

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

scholarly journals Energy-Efficient Ternary Multipliers Using CNT Transistors

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 643
Author(s):  
Sepehr Tabrizchi ◽  
Atiyeh Panahi ◽  
Fazel Sharifi ◽  
Hamid Mahmoodi ◽  
Abdel-Hameed A. Badawy
Keyword(s):  
Energy Consumption ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Approximate Computing ◽  
Digital Signals ◽  
Acceptable Error ◽  
Power Efficient ◽  
Multiple Valued Logic

In recent decades, power consumption has become an essential factor in attracting the attention of integrated circuit (IC) designers. Multiple-valued logic (MVL) and approximate computing are some techniques that could be applied to integrated circuits to make power-efficient systems. By utilizing MVL-based circuits instead of binary logic, the information conveyed by digital signals increases, and this reduces the required interconnections and power consumption. On the other hand, approximate computing is a class of arithmetic computing used in systems where the accuracy of the computation can be traded-off for lower energy consumption. In this paper, we propose novel designs for exact and inexact ternary multipliers based on carbon-nanotube field-effect transistors (CNFETs). The unique characteristics of CNFETs make them a desirable alternative to MOSFETs. The simulations are conducted using Synopsys HSPICE. The proposed design is compared against existing ternary multipliers. The results show that the proposed exact multiplier reduces the energy consumption by up to 6 times, while the best inexact design improves energy efficiency by up to 35 time compared to the latest state-of-the-art methods. Using the imprecise multipliers for image processing provides evidence that these proposed designs are a low-power system with an acceptable error.

Microtechnology

1978 ◽  
Vol 289 (1356) ◽  
pp. 93-101
Keyword(s):  
Single Crystal ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Telecommunications Industry ◽  
Electronic Circuits ◽  
Electronic Technology ◽  
System Designer ◽  
Silicon Technology ◽  
Process Engineer ◽  
The Future

The ability of the semiconductor industry to fabricate complex electronic circuits containing, say, 10000 components in a single crystal of silicon of dimensions 5 mm x 5 mm x 0.2 mm has become almost a commonplace, as the basis for semiconductor memories, microprocessors, calculators, electronic watches, etc. It has led to the concept of ‘the pervasiveness of silicon technology’. The purpose of this paper is to discuss how and why this technology has developed to date, and to consider the ways in which past trends are likely to continue in the next decade. In particular it suggests ways in which the skills of the telecommunications system designer and of the silicon process engineer need to be brought more closely together in the future in order to ensure that the telecommunications industry is able to make optimum use of this dominant field of electronic technology - the silicon integrated circuit.

scholarly journals Open innovation in the semiconductor industry: analysis of Brazilian design houses

2019 ◽  
Vol 17 (2) ◽  
pp. 133-156
Author(s):  
Xênia L'amour Campos Oliveira ◽  
Maria Elena Leon Olave ◽  
Edward David Moreno ◽  
Glessia Silva
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Open Innovation ◽  
Semiconductor Industry ◽  
Innovation Process ◽  
Research Strategy ◽  
Structured Interviews ◽  
Content Type ◽  
New Business ◽  
Multiple Case

Purpose This study aims to understand how Brazilian design houses (DHs) use open innovation in joint development projects for integrated circuits. Design/methodology/approach As a research strategy, qualitative research using multiple case studies was made. As sources of evidence, semi-structured interviews were conducted with three DHs of Programa integrated circuit [circuito integrado(CI)]-Brasil and with four specialists in the field, as well as analysis of documents. The data were analyzed through content analysis. Findings The results showed the DHs use sources of external knowledge in their innovation process, to assist the development of new products, to access new knowledge and skills, to attract financial resources and to be competitive in the market of high technology. Originality/value The study has important implications on the semiconductor industry in Brazil, as the industry is considered strategic for the competitiveness of final goods sector. The importance of encouraging the development of partnerships in the sector, the possibility of using informal agreements to mediate the collaboration between DHs and external agents, and the improvement and long-term continuity of public policies to support the industry are among the implications. In addition to suggestions for new business approaches to assist the strengthening of this segment.

scholarly journals Ultra-precision engineering in lithographic exposure equipment for the semiconductor industry

2012 ◽  
Vol 370 (1973) ◽  
pp. 3950-3972 ◽  
Author(s):  
Robert-H. Munnig Schmidt
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Atomic Scale ◽  
Precision Engineering ◽  
Exposure System ◽  
Moore’S Law ◽  
Moore's Law ◽  
Positioning Systems ◽  
Motion System ◽  
The Future

The developments in lithographic tools for the production of an integrated circuit (IC) are ruled by ‘Moore’s Law’: the density of components on an IC doubles in about every two years . The corresponding size reduction of the smallest detail in an IC entails several technological breakthroughs. The wafer scanner, the exposure system that defines those details, is the determining factor in these developments. This review deals with those aspects of the positioning systems inside these wafer scanners that enable the extension of Moore’s Law into the future. The design of these systems is increasingly difficult because of the accuracy levels in the sub-nanometre range coupled with motion velocities of several metres per second. In addition to the use of feedback control for the reduction of errors, high-precision model-based feed-forward control is required with an almost ideally reproducible motion-system behaviour and a strict limitation of random disturbing events. The full mastering of this behaviour even includes material drift on an atomic scale and is decisive for the future success of these machines.

Investigation of Using Contact and Non-contact Printing Technologies For Organic Transistor Fabrication

2002 ◽  
Vol 725 ◽  
Author(s):  
Jie Zhang ◽  
Paul Brazis ◽  
A. Roy Chowdhuri ◽  
John Szczech ◽  
Dan Gamota
Keyword(s):  
Integrated Circuits ◽  
Process Development ◽  
Field Effect Transistors ◽  
Low Cost ◽  
High Volume ◽  
Electrical Performance ◽  
Organic Polymer ◽  
Personal Area Networks ◽  
Material System ◽  
Contact Printing

AbstractLow cost, high volume manufacturing processes are envisioned for solution processable organic semiconductor integrated circuits (IC) fabrication. The organic IC may be the low cost solution for driving electronic devices, i.e. smart cards, RFID tags, flexible displays, personal area networks, and body area networks. This study investigated the manufacturability of organic electronics (organic field effect transistors (OFETs), organic light emitting diodes (OLEDs), etc.) using commercially available printing technologies and materials systems qualified for use in microelectronic products. The evaluated contact printing technologies were pad printing and screen-printing; the non-contact printing technologies were ink jetting and micro dispensing. The material system selection for transistor structures and active layers was based on printing technology requirements and commercial availability. The materials were polymer thick film conductors and insulators, conductive nano-particle suspensions, and organic polymer systems. A series of material property characterization and printing process development studies were conducted. Several OFET designs were created and functional all printed organic transistors were demonstrated. The device electrical performance was characterized.

Metallization for Integrated Circuit Manufacturing

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 33-37 ◽  
Author(s):  
R.V. Joshi ◽  
R.S. Blewer ◽  
S. Murarka
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Random Access ◽  
Circuit Performance ◽  
Integrated Circuit Manufacturing ◽  
The 1960S ◽  
Al Metallization

This issue of the MRS Bulletin focuses on current interconnect metallurgies practiced in the manufacturing of integrated circuits (ICs). The issue should serve as a reference for researchers, scientists, engineers, and those who are not familiar with the IC arena.Al-metallization requires special attention due to its wide usage in logic and memory circuits. Logic requirements drive technology toward improved circuit performance while memory improvements require high device and wiring densities. As the dynamic random access memory (DRAM) evolves from 64 Mbits to 256 Mbits, ultralarge-scale integrated (ULSI) wiring will decrease to below sub-0.3 μm in dimensions. Such circuits require robust, reliable back end of the line (BEOL) technology that meets high-performance, low-cost, stringent electromigration requirements. We feel that several of these emerging interconnect fabrication techniques have reached a sufficient level of maturity to warrant a reasonable exposition. We will concentrate on metallization systems in this issue, leaving a discussion of dielectrics for the future, due to space limitations.The semiconductor industry has relied on aluminum technology since the 1960s because it is a well-established, low-cost technology. Early improvements in the electromigration resistance of Al lines by the addition of Cu impurities after 1971 helped this metallurgy to endure further feature size reductions, without degradation of reliability. However, the relentless reduction in via and line size once again may bring into question the limitation of Al reliability. As a result, work on alternate low-resistivity and high-electromigration-resistant metals like Cu is continuing in parallel.

scholarly journals Bandstructure and Size-Scaling Effects in the Performance of Monolayer Black Phosphorus Nanodevices

Materials ◽  
2021 ◽  
Vol 15 (1) ◽  
pp. 243
Author(s):  
Mirko Poljak ◽  
Mislav Matić
Keyword(s):  
Integrated Circuits ◽  
Density Functional ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
Tight Binding ◽  
Black Phosphorus ◽  
Average Charge ◽  
Scaling Effects ◽  
Size Scaling ◽  
Technology Generation

Nanodevices based on monolayer black phosphorus or phosphorene are promising for future electron devices in high density integrated circuits. We investigate bandstructure and size-scaling effects in the electronic and transport properties of phosphorene nanoribbons (PNRs) and the performance of ultra-scaled PNR field-effect transistors (FETs) using advanced theoretical and computational approaches. Material and device properties are obtained by non-equilibrium Green’s function (NEGF) formalism combined with a novel tight-binding (TB) model fitted on ab initio density-functional theory (DFT) calculations. We report significant changes in the dispersion, number, and configuration of electronic subbands, density of states, and transmission of PNRs with nanoribbon width (W) downscaling. In addition, the performance of PNR FETs with 15 nm-long channels are self-consistently assessed by exploring the behavior of charge density, quantum capacitance, and average charge velocity in the channel. The dominant consequence of W downscaling is the decrease of charge velocity, which in turn deteriorates the ON-state current in PNR FETs with narrower nanoribbon channels. Nevertheless, we find optimum nanodevices with W > 1.4 nm that meet the requirements set by the semiconductor industry for the “3 nm” technology generation, which illustrates the importance of properly accounting bandstructure effects that occur in sub-5 nm-wide PNRs.

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