Double patterning overlay budget for 45 nm technology node single and double mask approach

2007 ◽  
Vol 25 (6) ◽  
pp. 2461 ◽  
Author(s):  
Pierluigi Rigolli ◽  
Catia Turco ◽  
Umberto Iessi ◽  
Gianfranco Capetti ◽  
Paolo Canestrari ◽  
...  
Keyword(s):  
Technology Node ◽  
Double Patterning

Process requirements for pitch splitting LELE double patterning at advanced logic technology node

2012 ◽  
Author(s):  
R. C. Peng ◽  
I. H. Huang ◽  
H. H. Liu ◽  
H. J. Lee ◽  
John Lin ◽  
...  
Keyword(s):  
Technology Node ◽  
Double Patterning

Sub-k1 = 0.25 lithography with double patterning technique for 45-nm technology node flash memory devices at λ = 193nm

2007 ◽  
Author(s):  
Gianfranco Capetti ◽  
Pietro Cantù ◽  
Elisa Galassini ◽  
Alessandro Vaglio Pret ◽  
Catia Turco ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Devices ◽  
Technology Node ◽  
Patterning Technique ◽  
Double Patterning

Double patterning overlay and CD budget for 32 nm technology node

2008 ◽  
Author(s):  
Umberto Iessi ◽  
Sara Loi ◽  
Antonio Salerno ◽  
Pierluigi Rigolli ◽  
Elio De Chiara ◽  
...  
Keyword(s):  
Technology Node ◽  
Double Patterning

Process variation challenges and resolution in the negative-tone develop double patterning for 20nm and below technology node

2015 ◽  
Author(s):  
Sohan S. Mehta ◽  
Lakshmi K. Ganta ◽  
Vikrant Chauhan ◽  
Yixu Wu ◽  
Sunil Singh ◽  
...  
Keyword(s):  
Process Variation ◽  
Technology Node ◽  
Double Patterning ◽  
Negative Tone

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node

2020 ◽  
Author(s):  
Semiu A. Olowogemo ◽  
Ahmed Yiwere ◽  
Bor-Tyng Lin ◽  
Hao Qiu ◽  
William H. Robinson ◽  
...  
Keyword(s):  
Technology Node ◽  
Cell Synthesis

Diffraction-based overlay for spacer patterning and double patterning technology

2011 ◽  
Author(s):  
Byoung Hoon Lee ◽  
JeongSu Park ◽  
Jongsu Lee ◽  
Sarohan Park ◽  
ChangMoon Lim ◽  
...  
Keyword(s):  
Double Patterning

Advanced CD Linearity Improvement for Multi-Project Wafers and SoC at 95 nm Technology Node

2002 ◽  
Author(s):  
Jeremy Lu ◽  
Nicole L. Sandlin ◽  
Hidetoshi Sato ◽  
Colbert Lu ◽  
Nicole Cheng ◽  
...  
Keyword(s):  
Technology Node ◽  
Linearity Improvement
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