Electrical characterization of silicon-on-insulator structures with a nondamaging elastic–metal gate

Author(s):  
Robert J. Hillard ◽  
William H. Howland ◽  
Louison C. Tan ◽  
Win Ye
2019 ◽  
Vol 28 (2) ◽  
pp. 157-169 ◽  
Author(s):  
Jerome Mitard ◽  
Benjamin Vincent ◽  
Brice De Jaeger ◽  
Raymond Krom ◽  
R. Loo ◽  
...  

1998 ◽  
Vol 264-268 ◽  
pp. 1097-1100 ◽  
Author(s):  
Peter Tobias ◽  
Shinji Nakagomi ◽  
A. Baranzahi ◽  
R. Zhu ◽  
Ingemar Lundström ◽  
...  

2001 ◽  
Vol 40 (Part 1, No. 9A) ◽  
pp. 5217-5220 ◽  
Author(s):  
Tsugunori Okumura ◽  
Kazuyoshi Eguchi ◽  
Aimin En ◽  
Michihiko Suhara

Author(s):  
Lim Soon Huat ◽  
Lwin Hnin-Ei ◽  
Vinod Narang ◽  
J.M. Chin

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.


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