Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

2007 ◽  
Vol 47 (4-5) ◽  
pp. 528-531 ◽  
Author(s):  
Ralf Endres ◽  
Yordan Stefanov ◽  
Udo Schwalke
2003 ◽  
Author(s):  
Hee Sung Kang ◽  
Wu-yun Quan ◽  
Kyung Soo Kim ◽  
Chang Bong Oh ◽  
Hyuk Ju Ryu ◽  
...  

MRS Bulletin ◽  
2002 ◽  
Vol 27 (3) ◽  
pp. 222-225 ◽  
Author(s):  
R. Degraeve ◽  
E. Cartier ◽  
T. Kauerauf ◽  
R. Carter ◽  
L. Pantisano ◽  
...  

AbstractThe continual scaling of complementary metal oxide semiconductor (CMOS) technologies has pushed the Si-SiO2 system to its very limits and has led to the consideration of a number of alternative high-ĸ gate dielectric materials. In the end, it will be the electrical properties of the new Si/high-ĸ system that will determine its usefulness in future CMOS generations. For this reason, the study of the electrical properties of high-ĸ gate insulators is crucial. We present an overview of some of the electrical characterization techniques and reliability tests used to evaluate possible high-ĸ gate materials. Most of these techniques are well known from the characterization of SiO2 layers, but there are some additional complications, such as the presence of several different layers within one gate stack or the use of different gate electrode materials. These make the interpretation and comparison of experimental results more troublesome.


2019 ◽  
Vol 28 (2) ◽  
pp. 157-169 ◽  
Author(s):  
Jerome Mitard ◽  
Benjamin Vincent ◽  
Brice De Jaeger ◽  
Raymond Krom ◽  
R. Loo ◽  
...  

2004 ◽  
Vol 146 (3) ◽  
pp. 355-358 ◽  
Author(s):  
J. Puigdollers ◽  
C. Voz ◽  
I. Martín ◽  
M. Vetter ◽  
A. Orpella ◽  
...  

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.


1998 ◽  
Vol 264-268 ◽  
pp. 1097-1100 ◽  
Author(s):  
Peter Tobias ◽  
Shinji Nakagomi ◽  
A. Baranzahi ◽  
R. Zhu ◽  
Ingemar Lundström ◽  
...  

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