Thin SiO[sub 2] layers on Si(111) with ultralow atomic step density

2000 ◽  
Vol 18 (6) ◽  
pp. 2862 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Atomic Step ◽  
Step Density

Dependence of Process Characteristics on Atomic-Step Density in Catalyst-Referred Etching of 4H–SiC(0001) Surface

2011 ◽  
Vol 11 (4) ◽  
pp. 2928-2930 ◽  
Author(s):  
Takeshi Okamoto ◽  
Yasuhisa Sano ◽  
Kazuma Tachibana ◽  
Kenta Arima ◽  
Azusa N. Hattori ◽  
...  
Keyword(s):  
Atomic Step ◽  
Process Characteristics ◽  
Step Density

Comparative Study of Interface Structure in GaAs/AlAs Superlattices By Tem and Raman Scattering

1987 ◽  
Vol 102 ◽  
Author(s):  
T. Nakamura ◽  
M. Ikeda ◽  
S. Muto ◽  
S. Komiya ◽  
I. Umebu
Keyword(s):  
Raman Scattering ◽  
Interface Structure ◽  
Atomic Step ◽  
Transition Layers ◽  
Bright Spots ◽  
Transmission Electron ◽  
Scattering Measurements ◽  
Step Density ◽  
Raman Characterization ◽  
Growth Temperature Dependence

ABSTRACTTransition layers in GaAs/AlAs superlattices were studied by high resolution transmission electron microscopy (HRTEM) observations and Raman scattering measurements. We clarified that arrays of bright spots at the interface in the TEM image is a good indicator of the interfacial configuration and that a high atomic step density with intervals of less than 10 nm is necessary for Raman characterization using confined LO phonons.We characterized the growth temperature dependence of the transition layers at the GaAs/AlAs interfaces. For a sample grown at 500'C, the extent of the transition layers is about one monolayer and that of the interfacial step intervals is more than 10 nm. For a sample grown at 700 0 C, these values are about two monolayers and less than 3 nm, respectively.

Surface and Interfacial Topography of Oxides on Si(111) With Ultra-Low Atomic Step Density

1999 ◽  
Vol 592 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Initial Step ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Oxide Surface ◽  
Atomic Step ◽  
Layer By Layer ◽  
Initial Oxidation ◽  
Atomic Steps ◽  
Si Substrates ◽  
Step Density

ABSTRACTAtomic force microscopy has been used to study the morphology of the oxide surface and the Si-SiO2 interface after oxidation of Si(111) surfaces that are either totally free of atomic steps or have well characterized low step density. The step-free areas were formed by thermally processing a patterned Si surface in which flat areas are enclosed by a square array of ridges; flow of the atomic steps into the surrounding ridge barriers produces a regular array of step-free areas each of which can be up to ∼50µm×50µm. Arrays of widely spaced steps (e.g. 5µm) can also be produced in the step-free areas. AFM scans of the same areas were taken prior to (dry) oxidation, after oxidation, and after chemical removal of the oxide. It was found that at an oxide thickness in the 5-13nm range, the initial step structure of the underlying Si substrates is translated through the oxide to the surface after oxidation with the oxide surface being somewhat rougher than the initial substrate. Furthermore, the initial step morphology of the substrate remains at the Si-SiO2 interface after etching away the oxide by HF. The interface roughness is less than that of the oxide surface. The results suggest that the initial oxidation of silicon proceeds in a ‘layer by layer’ manner and not through a preferential step-flow oxide growth mode.

scholarly journals Gypsum Dissolution Rate from Atomic Step Kinetics

2017 ◽  
Vol 121 (17) ◽  
pp. 9325-9330 ◽  
Author(s):  
Bahareh Zareeipolgardani ◽  
Agnès Piednoir ◽  
Jean Colombani
Keyword(s):  
Dissolution Rate ◽  
Atomic Step ◽  
Gypsum Dissolution

A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces

2002 ◽  
Vol 747 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Thermal Oxidation ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Oxide Surface ◽  
Interface Morphology ◽  
Device Structure ◽  
Atomic Steps ◽  
Surface And Interface ◽  
Step Density

ABSTRACTSurface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.

Atomic-Step-Induced Local Nonequilibrium Effects on Surface Oxidation

2017 ◽  
Vol 121 (41) ◽  
pp. 22846-22853 ◽  
Author(s):  
Hailang Qin ◽  
Xidong Chen ◽  
Jonathan Li ◽  
Peter Sutter ◽  
Guangwen Zhou
Keyword(s):  
Surface Oxidation ◽  
Atomic Step ◽  
Nonequilibrium Effects

Atomic step contrast from forbidden reflections

1985 ◽  
Vol 16 (1) ◽  
pp. 41-46 ◽  
Author(s):  
C.J. Rossouw ◽  
S.E. Donnelly ◽  
D.F. Lynch
Keyword(s):  
Atomic Step ◽  
Step Contrast
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