Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Hot Spots ◽  
High Performance ◽  
Thermal Environment ◽  
Hot Spot ◽  
Air Cooling ◽  
Multicore Processor ◽  
Temperature Contrast ◽  
On Chip ◽  
Heat Spreading ◽  
Level Analysis

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots

2009 ◽  
Author(s):  
Viatcheslav Litvinovitch ◽  
Avram Bar-Cohen
Keyword(s):  
Contact Resistance ◽  
Thermal Management ◽  
Hot Spots ◽  
High Performance ◽  
Thermal Contact Resistance ◽  
Hot Spot ◽  
Thermal Contact ◽  
Heat Fluxes ◽  
Thermoelectric Coolers ◽  
On Chip

Shrinking feature size and increasing transistor density, combined with the high performance demanded from next-generation microprocessors and other electronic components, have lead to the emergence of severe on-chip “hot spots,” with heat fluxes approaching — and at times exceeding — 1 kW/cm2. The cost-effective thermal management of such chips requires the introduction and refinement of novel cooling techniques. Mini-contact enhanced, miniaturized thermoelectric coolers (TECs) have been shown to be a viable approach for the remediation of on-chip hot spots, but their performance is constrained by the thermal resistance introduced by the attachment of this thermal management device. This paper uses a detailed finite-element package-level model to examine the parasitic effects of the thermal contact resistance (at the interfaces of the mini-contact and TEC) on the cooling efficacy of this thermal solution. Particular attention is devoted to the deleterious effect of contact resistance on the thermoelectric leg height and the mini-contact size required to achieve the greatest hot spot temperature reduction on the chip. Data from experiments with TECs (with a leg height of 130 μm) combined with several sizes of mini-contact pads, are used to validate the modeling approach and the overall conclusions.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang
Keyword(s):  
Heat Flux ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Microchannel Heat Sink ◽  
Three Dimensional Model ◽  
Spot Cooling ◽  
On Chip

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Silicon Hot Spot Remediation With a Germanium Self Cooling Layer

2011 ◽  
Author(s):  
Horacio Nochetto ◽  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Hot Spots ◽  
Hot Spot ◽  
Silicon Layer ◽  
Great Promise ◽  
Applied Current ◽  
Chip Cooling ◽  
Primary Driver ◽  
Germanium Layer ◽  
On Chip ◽  
Spot Temperature

Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.

Simplified Thermal Model of Silicon Thermoelectric Microcooler for On-Chip Hot Spot Remediation

2007 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Material Properties ◽  
Hot Spots ◽  
Hot Spot ◽  
Design Tool ◽  
The Novel ◽  
Thermo Electric ◽  
Design And Optimization ◽  
Conventional Cooling ◽  
On Chip

Thermal management of on-chip hot spots has become an increasing challenge in recent years because such localized high flux hot spots can not be effectively removed by conventional cooling techniques. The authors have recently explored the novel use of the silicon chip itself as a solid state thermoelectric micrcooler (μTEC) for hot spot thermal management. This paper describes the development and application of a thermo-electric design tool based on closed-form equations for the primary variables. This tool can be used to effectively reduce the complexity and required time for the design and optimization of the silicon microcooler geometry and material properties for on-chip hot spot remediation.

Array of Thermoelectric Coolers for On-Chip Thermal Management

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Owen Sullivan ◽  
Man Prakash Gupta ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Steady State ◽  
Current Pulse ◽  
Hot Spots ◽  
Hot Spot ◽  
High Amplitude ◽  
Peak Temperature ◽  
Thermoelectric Coolers ◽  
Electronic Package ◽  
Current Pulses ◽  
On Chip

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Adaptive Hot-Spot Cooling of Integrated Circuits Using Digital Microfluidics

2005 ◽  
Author(s):  
Phil Paik ◽  
Vamsee K. Pamula ◽  
Krishnendu Chakrabarty
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
High Performance ◽  
Cooling System ◽  
Hot Spot ◽  
Digital Microfluidics ◽  
Ic Design ◽  
Spot Cooling ◽  
Digital Microfluidic

Thermal management is becoming an increasingly important issue in integrated circuit (IC) design. The ability to cool ICs is quickly reaching a limit with today’s package-level solutions. While a number of novel cooling methods have been introduced, many of which are microfluidic approaches, these methods are unable to adaptively address the uneven thermal profiles and hot-spots generated in high performance ICs. In this paper, we present a droplet-based digital microfluidic cooling system for ICs that can adaptively cool hot-spots through real-time reprogrammable flow. This paper characterizes the effectiveness of microliter-sized droplets for cooling by determining the heat transfer coefficient of a droplet shuttling back and forth in an open system over a hot-spot at various speeds. Cooling is found to be significantly enhanced at higher flow rates of droplets. In order to further enhance cooling, the effect of varying droplet aspect ratio (width/height) in a confined system was also studied.

Hot Spot Cooling and Harvesting CPU Waste Heat Using Thermoelectric Modules

2014 ◽  
Author(s):  
Soochan Lee ◽  
Patrick E. Phelan ◽  
Carole-Jean Wu
Keyword(s):  
Energy Consumption ◽  
Hot Spots ◽  
Waste Heat ◽  
Hot Spot ◽  
Heat Energy ◽  
High Heat Flux ◽  
Air Cooling ◽  
Thermoelectric Coolers ◽  
Thermoelectric Modules ◽  
Spot Cooling

The increasing integration of high performance processors and dense circuits in current computing devices has produced high heat flux in localized areas (hot spots) that limits their performance and reliability. To control the hot spots on a CPU, many researchers have focused on active cooling methods such as thermoelectric coolers (TECs) to avoid thermal emergencies. This paper presents the optimized thermoelectric modules on top of the CPU combined with a conventional air-cooling device to reduce the hot spot temperature and at the same time harvest waste heat energy generated by the CPU. To control the temperature of the hot spots, we attach small-sized TECs to the CPU and use thermoelectric generators (TEGs) placed on the rest of the CPU to convert waste heat energy into electricity. This study investigates design alternatives with an analytical model considering the non-uniform temperature distribution based on two-node thermal networks. The results indicate that we are able to attain more energy from the TEGs than energy consumption for running the TECs. In other words, we can allow the harvested heat energy to be reused to power other components and reduce hot spots simultaneously. Overall, the idea of simultaneous hot spot cooling and waste heat harvesting using thermoelectric modules on a CPU is a promising method to control the problem of heat generation and to reduce energy consumption in a computing device.

Thermoelectric Self-Cooling on Germanium Chip

2010 ◽  
Author(s):  
Peng Wang ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Management ◽  
Hot Spots ◽  
Hot Spot ◽  
Thermal Contact ◽  
Chip Thickness ◽  
Management Approach ◽  
High Flux ◽  
Thermo Electric ◽  
Wide Range ◽  
On Chip

Growing interest in germanium solid-state devices is raising concern over the effects of on-chip, micro-scaled, high flux hot spot on the reliability and performance of germanium chips. Current thermal management technology offers few choices for such on-chip hot spot remediation. However, the good thermo-electric properties of single crystal germanium support the development of a novel thermal management approach, relying on thermoelectric self-cooling by an electric current flowing in a thin planar layer on the back of the germanium chip. Use of metal-on-germanium fabrication techniques can yield a very low thermal contact resistance at the micro cooler/chip interface and the current flow can transfer the energy absorbed from a hot spot to the edge of the chip, thus substantially reducing the detrimental effect of thermoelectric heating on the temperature of the active circuitry. In this paper three-dimensional thermo-electric simulations are used to investigate the self-cooling of hot spots on a germanium chip for a wide range of input current, doping concentration, hot spot heat flux, micro cooler size, and germanium chip thickness. Results suggest that localized thermoelectric self-cooling on the germanium chip can significantly reduce the temperature rise resulting from micro-scaled high-flux hot spots.

Thermal Management of Fujitsu High-End Unix Servers

2005 ◽  
Author(s):  
Jie Wei ◽  
Masahiro Suzuki
Keyword(s):  
Thermal Management ◽  
High Performance ◽  
Thermal Interface Materials ◽  
Air Cooling ◽  
Asymmetric Power ◽  
High Performance Computers ◽  
Interface Materials ◽  
Heat Spreading ◽  
System Packaging ◽  
Processor Module

An overview of system packaging and thermal management of the Fujitsu high-performance Unix server PRIMEPOWER HPC2500 is introduced in the present paper. Each node of the HPC2500 comprises sixteen system boards containing up to 128 SPARC64V CPU processors, with the maximum power dissipation about 30kW. A full configuration of the HPC2500 can be further scaled up to the maximum of 128 nodes, resulting in 16,384 CPU processors installed. Thermal management is introduced from viewpoints of the server-cabinet, system-board and CPU processor module levels, respectively. A design strategy of the forced convection air cooling scheme is outlined, implemented to meet increased demanding requirements of high density packaging, high power and power-density dissipations. Furthermore, thermal challenges, arising from high asymmetric power distributions and dissipations of CPU processors, are investigated for high performance computers. Temperature distributions of the CPU processors, effects of heat spreading materials (HIS) and impacts of thermal interface materials (TIM) on the cooling and packaging designs are also analysed and illustrated.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.

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