Design and Fabrication of a Temperature Sensor Based on Thermopile in CMOS Technology

2003 ◽  
Author(s):  
Ioana Voiculescu ◽  
Mona Zaghloul ◽  
R. Andrew McGill
Keyword(s):  
Temperature Sensor ◽  
Silicon Oxide ◽  
Mechanical Stability ◽  
Cmos Technology ◽  
Nitride Layer ◽  
Design Parameters ◽  
Cmos Process ◽  
Post Processing ◽  
Test Chip ◽  
Optimal Geometry

This paper describes a new geometry for integrated micromachined thermopile structures. Different arrangements for the thermocouples in proximity to the heating element are examined, to optimize the accuracy of the temperature measurement. Several design parameters including thermopile lengths, and the number of thermocouples, are examined. The test chip was designed and fabricated in CMOS technology, including the appropriate opening for post-processing micromachining. The thermopile used was fabricated with polysilicon/aluminum contacts on a silicon oxide/nitride layer provided by the CMOS process. Different microbeam and bridge membrane support structures were designed for the thermopile, in order to investigate the optimal geometry for mechanical stability and to avoid structure buckling.

scholarly journals Modellierungskonzept für MOS Varaktoren zur Minimierung der AM-FM Konversion in VCOs

2010 ◽  
Vol 8 ◽  
pp. 143-149
Author(s):  
T. Peikert ◽  
J.-K. Bremer ◽  
W. Mathis
Keyword(s):  
Simulation Model ◽  
Cmos Technology ◽  
Design Flow ◽  
Design Parameters ◽  
Cmos Process ◽  
Large Signal ◽  
Analytical Simulation ◽  
Good Accordance ◽  
Transistor Model ◽  
Lc Tank

Abstract. In dieser Arbeit wird ein analytisches Simulationsmodell für MOS Varaktoren zur Entwurfsunterstützung von integrierten CMOS LC-Tank VCO-Schaltungen präsentiert. Das analytische Simulationsmodell wurde auf Basis des EKV-Transistormodells implementiert und beinhaltet ausschließlich Design- und Prozessparameter für die Berechnung der Varaktorkapazität. Dieses Simulationsmodell ermöglicht es, die verwendeten Varaktoren im Vorfeld des VCO-Entwurfs zu dimensionieren, die effektive Großsignalkapazität in Abhängigkeit des Ausgangssignals zu berechnen und einzelne Eigenschaften der Varaktoren, wie z.B. das AM-FM Konversionsverhalten zu optimieren. Die Gültigkeit des vorgestellten analytischen Simulationsmodells zur Beschreibung der Varaktorkapazität in CMOS LC-Tank VCOs, wird anhand von Spectre (Cadence) Simulationen auf Basis eines 0.25 μm CMOS Prozesses der Firma IHP (SGB25) und eines 0.35 μm CMOS Prozesses der Firma AMS (C35) verifiziert. In this work an analytical simulation model for MOS varactors, that can be used in a systematically VCO design flow, is presented. The simulation model is based on the EKV transistor model and includes only design and process parameters of the used CMOS technology. The proposed simulation model allows calculating the required design parameters and the effective large signal capacitance of the varactors incorporated into the VCO as a function of the output signal of the VCO. Based on the expression for the effective large signal capacitance it is possible to optimize the AM-FM conversion behavior of the used varactors. The validity and accuracy of the simulation model is verified by Spectre simulations which are based on a 0.25 μm CMOS process (SGB25) from the company IHP and a 0.35 μm CMOS process (C35) from the company AMS. The simulation results show a good accordance in all transistor operating regions for NMOS varactors as well as PMOS varactors.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

scholarly journals Silicon photonic temperature sensor
employing a ring resonator manufactured
using a standard CMOS process

2010 ◽  
Vol 18 (21) ◽  
pp. 22215 ◽  
Author(s):  
Gun-Duk Kim ◽  
Hak-Soon Lee ◽  
Chang-Hyun Park ◽  
Sang-Shin Lee ◽  
Boo Tak Lim ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Ring Resonator ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Silicon Photonic

A CMOS Temperature Sensor with a Maximum Accuracy of 1.6 °C after One-Point Calibration

2013 ◽  
Vol 336-338 ◽  
pp. 216-220
Author(s):  
Chun Chi Chen ◽  
Keng Chih Liu ◽  
Shih Hao Lin
Keyword(s):  
Temperature Sensor ◽  
Pulse Generator ◽  
Circuit Complexity ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Chip Area ◽  
Test Cost Reduction ◽  
Linear Delay ◽  
Time Amplifier ◽  
Fine Resolution

This paper presents a time-domain CMOS oscillator-based temperature sensor with one-point calibration for test cost reduction. Compared with the former CMOS sensors with linear delay lines, the proposed work composed of a temperature-to-pulse generator with adjustable time gain and a time-to-digital converter (TDC) can achieve lower circuit complexity and smaller area. A temperature-dependent oscillator for temperature sensing was used to generate the period width proportional to absolute temperature (PTAT). With the help of calibration circuit, an adjustable-gain time amplifier was adopted to dynamically adjust the amplified width that was converted by the TDC into the corresponding digital code. After calibration, the fluctuation of the sensor output with process variation can be greatly reduced. The maximum inaccuracy after one-point calibration for six package chips was 1.6 °C within a 0 80 °C temperature range. The proposed sensor fabricated in a 0.35-μm CMOS process occupied a chip area of merely 0.07 mm2, achieved a fine resolution of 0.047 °C/LSB, and consumed a low power of 25 μW@10 samples/s.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

scholarly journals Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 436 ◽  
Author(s):  
Chin-An Hsieh ◽  
Chia-Ming Tsai ◽  
Bing-Yue Tsui ◽  
Bo-Jen Hsiao ◽  
Sheng-Di Lin
Keyword(s):  
Detection Probability ◽  
Single Photon ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Single Photons ◽  
Photon Detection ◽  
Important Indicator ◽  
Avalanche Diodes ◽  
Single Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.

scholarly journals A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2198
Author(s):  
Zhichao Li ◽  
Shiheng Yang ◽  
Samuel B. S. Lee ◽  
Kiat Seng Yeo
Keyword(s):  
Output Power ◽  
Effective Conductivity ◽  
Building Blocks ◽  
Cmos Technology ◽  
Center Frequency ◽  
Cmos Process ◽  
Two Stage ◽  
Power Added Efficiency ◽  
X Band ◽  
Compact Size

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

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